d7eebd9227
as used on later arm26 system (A5000, A4, A3010, A3020, A4000). What we have got: ... upc0 at iobus0 base 0x010000: config state bb 87 1c 00 00 fdc at upc0 offset 0x3f4 not configured wdc0 at upc0 offset 0x1f0 lpt0 at upc0 offset 0x278 com0 at upc0 offset 0x3f8: ns8250 or ns16450, no fifo ... What we haven't got: - FDC support (found, but not configured). - Clearing lpt interrupts on arm26 systems (needs help from IOEB). - A upc(4) manual page. - More than minimal testing (my A3020s don't have root devices). - A proper probe routine (arm26 can't use one anyway).
95 lines
4.1 KiB
C
95 lines
4.1 KiB
C
/* $NetBSD: upcreg.h,v 1.2 2000/08/16 23:56:12 bjh21 Exp $ */
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/*
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* Ben Harris, 2000
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*
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* This file is in the public domain.
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*/
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/*
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* upcreg.h - CHIPS and Technologies Universal Peripheral Controllers
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*/
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/*
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* This file contains register details for:
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* CHIPS 82C710 Universal Peripheral Controller
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* CHIPS 82C711 Universal Peripheral Controller II
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* CHIPS 82C721 Universal Peripheral Controller III
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*/
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#define UPC_BUS_SIZE 0x400 /* Approximate */
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/* Fixed port addresses */
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#define UPC_PORT_CFGADDR 0x3f0 /* Configuration register address */
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#define UPC_PORT_CFGDATA 0x3f1 /* Configuration register value */
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#define UPC_PORT_IDECMDBASE 0x1f0 /* IDE primary base */
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#define UPC_PORT_IDECTLBASE 0x3f6 /* IDE secondary base */
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#define UPC_PORT_FDCBASE 0x3f4 /* FDC base address (82C721 only) */
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#define UPC_PORT_GAME 0x201 /* -GAMECS active */
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/* Configuration magic sequences */
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#define UPC_CFGMAGIC_ENTER 0x55 /* Write twice to enter config mode. */
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#define UPC_CFGMAGIC_EXIT 0xaa /* Write once to exit config mode. */
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/* Configuration registers */
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#define UPC_CFGADDR_CR0 0x00 /* Configuration Register 0 */
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#define UPC_CFGADDR_CR1 0x01 /* Configuration Register 1 */
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#define UPC_CFGADDR_CR2 0x02 /* Configuration Register 2 */
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#define UPC_CFGADDR_CR3 0x03 /* Configuration Register 3 */
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#define UPC_CFGADDR_CR4 0x04 /* Configuration Register 4 */
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/* Configuration register 0 */
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#define UPC_CR0_VALID 0x80 /* Device has been configured */
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#define UPC_CR0_OSC_MASK 0x60 /* Oscillator control */
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#define UPC_CR0_OSC_ON 0x00 /* Oscillator always on */
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#define UPC_CR0_OSC_PWRGD 0x20 /* Oscillator on when PWRGD */
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#define UPC_CR0_OSC_OFF 0x60 /* Oscillator always off */
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#define UPC_CR0_FDC_ENABLE 0x10 /* FDC enabled */
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#define UPC_CR0_FDC_ON 0x08 /* FDC powered */
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#define UPC_CR0_IDE_AT 0x02 /* IDE controller is AT type */
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#define UPC_CR0_IDE_ENABLE 0x01 /* IDE controller enabled */
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/* Configuration register 1 */
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#define UPC_CR1_READ_ENABLE 0x80 /* Enable reading of config regs */
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#define UPC_CR1_COM34_MASK 0x60 /* COM3/COM4 addresses */
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#define UPC_CR1_COM34_338_238 0x00 /* COM3 = 0x338; COM4 = 0x238 */
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#define UPC_CR1_COM34_3E8_2E8 0x20 /* COM3 = 0x3E8; COM4 = 0x2E8 */
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#define UPC_CR1_COM34_2E8_2E0 0x40 /* COM3 = 0x2E8; COM4 = 0x2E0 */
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#define UPC_CR1_COM34_220_228 0x60 /* COM3 = 0x220; COM4 = 0x228 */
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#define UPC_CR1_IRQ_ACTHIGH 0x10 /* IRQ is active-high */
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#define UPC_CR1_LPT_BORING 0x08 /* Parallel port is not EPP */
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#define UPC_CR1_LPT_ON 0x04 /* Parallel port is powered */
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#define UPC_CR1_LPT_MASK 0x03 /* Parallel port address */
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#define UPC_CR1_LPT_DISABLE 0x00 /* Parallel port disabled */
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#define UPC_CR1_LPT_3BC 0x01 /* Parallel port at 0x3BC */
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#define UPC_CR1_LPT_378 0x02 /* Parallel port at 0x378 */
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#define UPC_CR1_LPT_278 0x03 /* Parallel port at 0x278 */
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/* Configuration register 2 */
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/* I believe 2ndary serial is absent on 82C710 */
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#define UPC_CR2_UART2_ON 0x80 /* 2ndary serial powered */
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#define UPC_CR2_UART2_ENABLE 0x40 /* 2ndary serial enabled */
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#define UPC_CR2_UART2_MASK 0x30 /* 2ndary serial address */
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#define UPC_CR2_UART2_3F8 0x00 /* 2ndary serial at 0x3F8 */
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#define UPC_CR2_UART2_2F8 0x10 /* 2ndary serial at 0x2F8 */
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#define UPC_CR2_UART2_COM3 0x20 /* 2ndary serial at COM3 (see CR1) */
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#define UPC_CR2_UART2_COM4 0x30 /* 2ndary serial at COM4 (see CR1) */
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#define UPC_CR2_UART1_ON 0x08 /* primary serial powered */
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#define UPC_CR2_UART1_ENABLE 0x04 /* primary serial enabled */
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#define UPC_CR2_UART1_MASK 0x03 /* primary serial address */
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#define UPC_CR2_UART1_3F8 0x00 /* primary serial at 0x3F8 */
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#define UPC_CR2_UART1_2F8 0x01 /* primary serial at 0x2F8 */
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#define UPC_CR2_UART1_COM3 0x02 /* primary serial at COM3 (see CR1) */
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#define UPC_CR2_UART1_COM4 0x03 /* primary serial at COM4 (see CR1) */
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/* Configuration register 3 */
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#define UPC_CR3_UART2_TEST 0x80 /* 2ndary serial test mode */
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#define UPC_CR3_UART1_TEST 0x40 /* primary serial test mode */
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#define UPC_CR3_FDC_TEST_MASK 0x30 /* FDC test modes */
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#define UPC_CR3_FDC_TEST_NORMAL 0x00 /* FDC normal mode */
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/* Configuration register 4 (82C721 only) */
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#define UPC_CR4_UART2_DIV13 0x01 /* Use normal (cf MIDI) clock for UART2 */
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