423 lines
11 KiB
C
423 lines
11 KiB
C
/* $NetBSD: ioasic.c,v 1.24 1999/04/10 01:21:38 cgd Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Keith Bostic, Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include "opt_dec_3000_300.h"
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.24 1999/04/10 01:21:38 cgd Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/pte.h>
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#include <machine/rpb.h>
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#ifndef EVCNT_COUNTERS
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#include <machine/intrcnt.h>
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#endif
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#include <dev/tc/tcvar.h>
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#include <alpha/tc/ioasicreg.h>
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#include <dev/tc/ioasicvar.h>
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/* Definition of the driver for autoconfig. */
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int ioasicmatch __P((struct device *, struct cfdata *, void *));
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void ioasicattach __P((struct device *, struct device *, void *));
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struct cfattach ioasic_ca = {
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sizeof(struct ioasic_softc), ioasicmatch, ioasicattach,
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};
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int ioasic_intr __P((void *));
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int ioasic_intrnull __P((void *));
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#define C(x) ((void *)(x))
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#define IOASIC_DEV_LANCE 0
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#define IOASIC_DEV_SCC0 1
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#define IOASIC_DEV_SCC1 2
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#define IOASIC_DEV_ISDN 3
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#define IOASIC_DEV_BOGUS -1
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#define IOASIC_NCOOKIES 4
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struct ioasic_dev ioasic_devs[] = {
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/* XXX lance name */
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{ "lance", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE),
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IOASIC_INTR_LANCE, },
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{ "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0),
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IOASIC_INTR_SCC_0, },
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{ "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1),
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IOASIC_INTR_SCC_1, },
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{ "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS),
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0, },
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{ "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN),
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IOASIC_INTR_ISDN, },
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};
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int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]);
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struct ioasicintr {
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int (*iai_func) __P((void *));
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void *iai_arg;
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} ioasicintrs[IOASIC_NCOOKIES];
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tc_addr_t ioasic_base; /* XXX XXX XXX */
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/* There can be only one. */
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int ioasicfound;
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/*
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* DMA area for IOASIC LANCE.
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* XXX Should be done differently, but this is better than it used to be.
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*/
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#define LE_IOASIC_MEMSIZE (128*1024)
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#define LE_IOASIC_MEMALIGN (128*1024)
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caddr_t le_iomem;
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void ioasic_lance_dma_setup __P((struct ioasic_softc *));
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int
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ioasicmatch(parent, cfdata, aux)
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struct device *parent;
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struct cfdata *cfdata;
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void *aux;
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{
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struct tc_attach_args *ta = aux;
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/* Make sure that we're looking for this type of device. */
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if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN))
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return (0);
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/* Check that it can actually exist. */
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if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300))
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panic("ioasicmatch: how did we get here?");
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if (ioasicfound)
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return (0);
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return (1);
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}
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void
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ioasicattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct ioasic_softc *sc = (struct ioasic_softc *)self;
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struct tc_attach_args *ta = aux;
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struct ioasicdev_attach_args ioasicdev;
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u_long i;
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ioasicfound = 1;
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sc->sc_base = ta->ta_addr;
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ioasic_base = sc->sc_base; /* XXX XXX XXX */
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sc->sc_cookie = ta->ta_cookie;
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sc->sc_dmat = ta->ta_dmat;
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#ifdef DEC_3000_300
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if (cputype == ST_DEC_3000_300) {
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*(volatile u_int *)IOASIC_REG_CSR(sc->sc_base) |=
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IOASIC_CSR_FASTMODE;
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tc_mb();
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printf(": slow mode\n");
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} else
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#endif
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printf(": fast mode\n");
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/*
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* Turn off all device interrupt bits.
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* (This does _not_ include 3000/300 TC option slot bits.
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*/
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for (i = 0; i < ioasic_ndevs; i++)
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*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
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~ioasic_devs[i].iad_intrbits;
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tc_mb();
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/*
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* Set up interrupt handlers.
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*/
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for (i = 0; i < IOASIC_NCOOKIES; i++) {
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ioasicintrs[i].iai_func = ioasic_intrnull;
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ioasicintrs[i].iai_arg = (void *)i;
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}
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tc_intr_establish(parent, sc->sc_cookie, TC_IPL_NONE, ioasic_intr, sc);
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/*
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* Set up the LANCE DMA area.
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*/
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ioasic_lance_dma_setup(sc);
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/*
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* Try to configure each device.
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*/
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for (i = 0; i < ioasic_ndevs; i++) {
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strncpy(ioasicdev.iada_modname, ioasic_devs[i].iad_modname,
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TC_ROM_LLEN);
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ioasicdev.iada_modname[TC_ROM_LLEN] = '\0';
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ioasicdev.iada_offset = ioasic_devs[i].iad_offset;
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ioasicdev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset;
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ioasicdev.iada_cookie = ioasic_devs[i].iad_cookie;
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/* Tell the autoconfig machinery we've found the hardware. */
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config_found(self, &ioasicdev, ioasicprint);
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}
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}
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void
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ioasic_intr_establish(ioa, cookie, level, func, arg)
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struct device *ioa;
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void *cookie, *arg;
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tc_intrlevel_t level;
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int (*func) __P((void *));
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{
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u_long dev, i;
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dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX check cookie. */
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#endif
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if (ioasicintrs[dev].iai_func != ioasic_intrnull)
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panic("ioasic_intr_establish: cookie %lu twice", dev);
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ioasicintrs[dev].iai_func = func;
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ioasicintrs[dev].iai_arg = arg;
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/* Enable interrupts for the device. */
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for (i = 0; i < ioasic_ndevs; i++)
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if (ioasic_devs[i].iad_cookie == cookie)
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break;
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if (i == ioasic_ndevs)
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panic("ioasic_intr_establish: invalid cookie.");
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*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) |=
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ioasic_devs[i].iad_intrbits;
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tc_mb();
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}
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void
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ioasic_intr_disestablish(ioa, cookie)
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struct device *ioa;
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void *cookie;
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{
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u_long dev, i;
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dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX check cookie. */
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#endif
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if (ioasicintrs[dev].iai_func == ioasic_intrnull)
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panic("ioasic_intr_disestablish: cookie %lu missing intr", dev);
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/* Enable interrupts for the device. */
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for (i = 0; i < ioasic_ndevs; i++)
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if (ioasic_devs[i].iad_cookie == cookie)
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break;
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if (i == ioasic_ndevs)
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panic("ioasic_intr_disestablish: invalid cookie.");
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*(volatile u_int32_t *)IOASIC_REG_IMSK(ioasic_base) &=
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~ioasic_devs[i].iad_intrbits;
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tc_mb();
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ioasicintrs[dev].iai_func = ioasic_intrnull;
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ioasicintrs[dev].iai_arg = (void *)dev;
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}
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int
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ioasic_intrnull(val)
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void *val;
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{
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panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld\n",
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(u_long)val);
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}
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/*
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* asic_intr --
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* ASIC interrupt handler.
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*/
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int
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ioasic_intr(val)
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void *val;
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{
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register struct ioasic_softc *sc = val;
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register int ifound;
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int gifound;
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u_int32_t sir;
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volatile u_int32_t *sirp;
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sirp = (volatile u_int32_t *)IOASIC_REG_INTR(sc->sc_base);
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gifound = 0;
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do {
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ifound = 0;
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tc_syncbus();
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sir = *sirp;
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#ifdef EVCNT_COUNTERS
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/* No interrupt counting via evcnt counters */
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XXX BREAK HERE XXX
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#else /* !EVCNT_COUNTERS */
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#define INCRINTRCNT(slot) intrcnt[INTRCNT_IOASIC + slot]++
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#endif /* EVCNT_COUNTERS */
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/* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */
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#define CHECKINTR(slot, bits) \
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if (sir & bits) { \
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ifound = 1; \
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INCRINTRCNT(slot); \
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(*ioasicintrs[slot].iai_func) \
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(ioasicintrs[slot].iai_arg); \
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}
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CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0);
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CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1);
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CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE);
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CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN);
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gifound |= ifound;
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} while (ifound);
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return (gifound);
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}
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/* XXX */
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char *
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ioasic_lance_ether_address()
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{
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return (u_char *)IOASIC_SYS_ETHER_ADDRESS(ioasic_base);
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}
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void
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ioasic_lance_dma_setup(sc)
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struct ioasic_softc *sc;
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{
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bus_dma_tag_t dmat = sc->sc_dmat;
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bus_dma_segment_t seg;
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volatile u_int32_t *ldp;
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tc_addr_t tca;
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int rseg;
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/*
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* Allocate a DMA area for the chip.
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*/
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if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN,
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0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
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printf("%s: can't allocate DMA area for LANCE\n",
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sc->sc_dv.dv_xname);
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return;
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}
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if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE,
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&le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) {
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printf("%s: can't map DMA area for LANCE\n",
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sc->sc_dv.dv_xname);
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bus_dmamem_free(dmat, &seg, rseg);
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return;
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}
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/*
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* Create and load the DMA map for the DMA area.
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*/
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if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1,
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LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_lance_dmam)) {
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printf("%s: can't create DMA map\n", sc->sc_dv.dv_xname);
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goto bad;
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}
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if (bus_dmamap_load(dmat, sc->sc_lance_dmam,
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le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) {
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printf("%s: can't load DMA map\n", sc->sc_dv.dv_xname);
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goto bad;
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}
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tca = (tc_addr_t)sc->sc_lance_dmam->dm_segs[0].ds_addr;
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if (tca != sc->sc_lance_dmam->dm_segs[0].ds_addr) {
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printf("%s: bad LANCE DMA address\n", sc->sc_dv.dv_xname);
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bus_dmamap_unload(dmat, sc->sc_lance_dmam);
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goto bad;
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}
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ldp = (volatile u_int *)IOASIC_REG_LANCE_DMAPTR(ioasic_base);
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*ldp = ((tca << 3) & ~(tc_addr_t)0x1f) | ((tca >> 29) & 0x1f);
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tc_wmb();
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*(volatile u_int32_t *)IOASIC_REG_CSR(ioasic_base) |=
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IOASIC_CSR_DMAEN_LANCE;
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tc_mb();
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return;
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bad:
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bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE);
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bus_dmamem_free(dmat, &seg, rseg);
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le_iomem = 0;
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}
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