508883c164
Cardbus_conf_{read,write}() instead of cardbus_conf_{read,write}().
Delete all of the CARDBUS_ constants and macros that replicate PCI_.
Compile-tested, only.
321 lines
9.6 KiB
C
321 lines
9.6 KiB
C
/* $NetBSD: siisata_cardbus.c,v 1.10 2010/02/26 00:57:02 dyoung Exp $ */
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/* Id: siisata_pci.c,v 1.11 2008/05/21 16:20:11 jakllsch Exp */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Copyright (c) 2007, 2008 Jonathan A. Kollasch.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: siisata_cardbus.c,v 1.10 2010/02/26 00:57:02 dyoung Exp $");
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <uvm/uvm_extern.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/ic/siisatavar.h>
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struct siisata_cardbus_softc {
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struct siisata_softc si_sc;
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cardbus_chipset_tag_t sc_cc;
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cardbus_function_tag_t sc_cf;
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cardbus_devfunc_t sc_ct;
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pcitag_t sc_tag;
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bus_space_tag_t sc_iot; /* CardBus I/O space tag */
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bus_space_tag_t sc_memt; /* CardBus MEM space tag */
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#if rbus
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rbus_tag_t sc_rbus_iot; /* CardBus i/o rbus tag */
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rbus_tag_t sc_rbus_memt; /* CardBus mem rbus tag */
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#endif
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bus_size_t sc_grsize;
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bus_size_t sc_prsize;
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void *sc_ih;
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};
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static int siisata_cardbus_match(device_t, cfdata_t, void *);
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static void siisata_cardbus_attach(device_t, device_t, void *);
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static int siisata_cardbus_detach(device_t, int);
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static bool siisata_cardbus_resume(device_t, const pmf_qual_t *);
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static const struct siisata_cardbus_product {
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pci_vendor_id_t scp_vendor;
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pci_product_id_t scp_product;
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int scp_ports;
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int scp_chip;
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} siisata_cardbus_products[] = {
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{
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PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3124,
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4, 3124
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},
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{
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0, 0,
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0, 0
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},
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};
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CFATTACH_DECL_NEW(siisata_cardbus, sizeof(struct siisata_cardbus_softc),
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siisata_cardbus_match, siisata_cardbus_attach, siisata_cardbus_detach,
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NULL);
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static const struct siisata_cardbus_product *
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siisata_cardbus_lookup(const struct cardbus_attach_args *ca)
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{
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const struct siisata_cardbus_product *scp;
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for (scp = siisata_cardbus_products; scp->scp_ports > 0; scp++) {
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if (PCI_VENDOR(ca->ca_id) == scp->scp_vendor &&
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PCI_PRODUCT(ca->ca_id) == scp->scp_product)
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return scp;
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}
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return NULL;
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}
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static int
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siisata_cardbus_match(device_t parent, cfdata_t match, void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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if (siisata_cardbus_lookup(ca) != NULL)
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return 3;
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return 0;
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}
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static void
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siisata_cardbus_attach(device_t parent, device_t self, void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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struct siisata_cardbus_softc *csc = device_private(self);
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struct siisata_softc *sc = &csc->si_sc;
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cardbus_devfunc_t ct = ca->ca_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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pcireg_t csr;
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const struct siisata_cardbus_product *scp;
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bus_space_tag_t memt;
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bus_space_handle_t memh;
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bus_addr_t base;
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bus_size_t grsize, prsize;
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uint32_t gcreg;
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char devinfo[256];
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sc->sc_atac.atac_dev = self;
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csc->sc_cc = cc;
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csc->sc_cf = cf;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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csc->sc_iot = ca->ca_iot;
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csc->sc_memt = ca->ca_memt;
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#if rbus
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csc->sc_rbus_iot = ca->ca_rbus_iot;
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csc->sc_rbus_memt = ca->ca_rbus_memt;
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#endif
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pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo));
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aprint_naive(": SATA-II HBA\n");
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aprint_normal(": %s\n", devinfo);
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/*
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* XXXX
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* Our BAR0/BAR1 type is 64bit Memory. Cardbus_mapreg_map() don't
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* support 64bit Memory. We map ourself...
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*/
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/* map bar0 */
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{
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#define SIISATA_BAR0_SIZE 128
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grsize = SIISATA_BAR0_SIZE;
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csr =
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Cardbus_conf_read(ct, ca->ca_tag, SIISATA_CARDBUS_BAR0);
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base = PCI_MAPREG_MEM_ADDR(csr);
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memt = csc->sc_memt;
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if ((*cf->cardbus_space_alloc)(cc, csc->sc_rbus_memt, base,
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grsize, grsize - 1, grsize, 0, &base, &memh)) {
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aprint_error(
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"%s: unable to map device global registers\n",
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SIISATANAME(sc));
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return;
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}
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Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR0,
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base);
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}
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sc->sc_grt = memt;
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sc->sc_grh = memh;
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csc->sc_grsize = grsize;
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/* map bar1 */
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{
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#define SIISATA_BAR1_SIZE (32 * 1024)
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prsize = SIISATA_BAR1_SIZE;
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base = PCI_MAPREG_MEM_ADDR(Cardbus_conf_read(ct, ca->ca_tag,
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SIISATA_CARDBUS_BAR1));
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memt = csc->sc_memt;
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if ((*cf->cardbus_space_alloc)(cc, csc->sc_rbus_memt, base,
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prsize, prsize - 1, prsize, 0, &base, &memh)) {
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Cardbus_conf_write(ct, ca->ca_tag,
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SIISATA_CARDBUS_BAR0, 0);
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(*cf->cardbus_space_free)(cc, csc->sc_rbus_memt,
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sc->sc_grh, grsize);
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aprint_error(
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"%s: unable to map device port registers\n",
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SIISATANAME(sc));
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return;
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}
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Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR1,
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base);
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}
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sc->sc_prt = memt;
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sc->sc_prh = memh;
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csc->sc_prsize = prsize;
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sc->sc_dmat = ca->ca_dmat;
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/* map interrupt */
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csc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
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siisata_intr, sc);
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if (csc->sc_ih == NULL) {
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Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR0, 0);
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(*cf->cardbus_space_free)(cc, csc->sc_rbus_memt, sc->sc_grh,
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grsize);
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Cardbus_conf_write(ct, ca->ca_tag, SIISATA_CARDBUS_BAR1, 0);
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(*cf->cardbus_space_free)(cc, csc->sc_rbus_memt, sc->sc_prh,
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prsize);
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aprint_error("%s: couldn't establish interrupt\n",
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SIISATANAME(sc));
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return;
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}
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/* fill in number of ports on this device */
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scp = siisata_cardbus_lookup(ca);
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if (scp != NULL)
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sc->sc_atac.atac_nchannels = scp->scp_ports;
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else
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/* _match() should prevent us from getting here */
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panic("siisata: the universe might be falling apart!\n");
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/* enable bus mastering in case the firmware didn't */
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csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_MASTER_ENABLE;
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csr |= PCI_COMMAND_MEM_ENABLE;
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Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, csr);
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gcreg = GRREAD(sc, GR_GC);
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/* CardBus supports only 32-bit 33MHz */
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KASSERT(!(gcreg &
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(GR_GC_REQ64|GR_GC_DEVSEL|GR_GC_STOP|GR_GC_TRDY|GR_GC_M66EN)));
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aprint_normal("%s: SiI%d on 32-bit, 33MHz PCI (CardBus).",
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SIISATANAME(sc), scp->scp_chip);
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if (gcreg & GR_GC_3GBPS)
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aprint_normal(" 3.0Gb/s capable.\n");
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else
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aprint_normal("\n");
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siisata_attach(sc);
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if (!pmf_device_register(self, NULL, siisata_cardbus_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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static int
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siisata_cardbus_detach(device_t self, int flags)
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{
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struct siisata_cardbus_softc *csc = device_private(self);
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struct siisata_softc *sc = &csc->si_sc;
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struct cardbus_devfunc *ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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pcitag_t ctag = csc->sc_tag;
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int rv;
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rv = siisata_detach(sc, flags);
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if (rv)
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return (rv);
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if (csc->sc_ih != NULL) {
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cardbus_intr_disestablish(csc->sc_cc, csc->sc_cf, csc->sc_ih);
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csc->sc_ih = NULL;
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}
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if (csc->sc_grsize) {
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Cardbus_conf_write(ct, ctag, SIISATA_CARDBUS_BAR0, 0);
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(*cf->cardbus_space_free)(cc, csc->sc_rbus_memt, sc->sc_grh,
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csc->sc_grsize);
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csc->sc_grsize = 0;
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}
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if (csc->sc_prsize) {
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Cardbus_conf_write(ct, ctag, SIISATA_CARDBUS_BAR1, 0);
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(*cf->cardbus_space_free)(cc, csc->sc_rbus_memt, sc->sc_prh,
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csc->sc_prsize);
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csc->sc_prsize = 0;
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}
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return 0;
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}
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static bool
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siisata_cardbus_resume(device_t dv, const pmf_qual_t *qual)
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{
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struct siisata_cardbus_softc *csc = device_private(dv);
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struct siisata_softc *sc = &csc->si_sc;
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int s;
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s = splbio();
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siisata_resume(sc);
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splx(s);
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return true;
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}
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