164 lines
5.0 KiB
C
164 lines
5.0 KiB
C
/* $NetBSD: pte.h,v 1.4 2002/12/06 10:10:48 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH5 Page Table Entry
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*/
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#ifndef _SH5_PTE_H
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#define _SH5_PTE_H
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/*
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* The size of the in-core copy of the PTE registers depends on the
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* number of valid effective address bits.
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* This is purely a memory-saving exercise.
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*/
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#if SH5_NEFF_BITS > 32
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typedef u_int64_t pteh_t;
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typedef u_int64_t ptel_t;
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#else
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typedef u_int32_t pteh_t;
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typedef u_int32_t ptel_t;
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#endif
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typedef u_int16_t vsid_t;
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typedef u_int16_t tlbcookie_t;
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/*
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* The in-core PTE for user mappings
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*
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* XXX: Don't change the ordering of this structure. XXX
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*/
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typedef struct pte {
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volatile ptel_t ptel;
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volatile tlbcookie_t tlbcookie;
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vsid_t vsid;
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pteh_t pteh;
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} pte_t;
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/*
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* The in-core PTE for kernel (KSEG1) mappings.
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*
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* Note: This structure must match the first two items of the userland
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* PTE structure.
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*
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* Note#2: Use pmap_kernel_ipt_{set,get}_{ptel,tlbcookie}() to access
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* members of the following structure. The compiler generates lousy
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* code otherwise.
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*/
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typedef struct kpte {
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volatile ptel_t ptel;
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volatile tlbcookie_t tlbcookie;
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} __attribute__ ((__packed__)) kpte_t;
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/*
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* Hardware fields in a pteh_t
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*
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* This is what a PTEH looks like when it is in the TLB.
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* Note that the pmap module uses the ASID field to store metadata
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* for in-core copies of PTEHs.
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*/
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#define SH5_PTEH_V (1 << 0) /* Valid */
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#define SH5_PTEH_SH (1 << 1) /* Shared mapping */
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#define SH5_PTEH_ASID_SHIFT 2
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#define SH5_PTEH_ASID_SIZE (1 << SH5_ASID_BITS)
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#define SH5_PTEH_ASID_MASK (SH5_PTEH_ASID_SIZE - 1)
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#define SH5_PTEH_EPN_SHIFT 12
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#if SH5_NEFF_BITS == 32
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#define SH5_PTEH_EPN_MASK 0xfffff000UL
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#else
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#define SH5_PTEH_EPN_MASK 0xfffffffffffff000UL
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#endif
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/*
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* Hardware fields in a ptel_t
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*
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* This is what a PTEH looks like when it is in the TLB.
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*/
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#define SH5_PTEL_CB_MASK 0x3
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#define SH5_PTEL_CB_NOCACHE 0x0
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#define SH5_PTEL_CB_DEVICE 0x1
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#define SH5_PTEL_CB_WRITEBACK 0x2
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#define SH5_PTEL_CB_WRITETHRU 0x3
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#define SH5_PTEL_CACHEABLE(p) (((p)&SH5_PTEL_CB_MASK)>=SH5_PTEL_CB_WRITEBACK)
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#define SH5_PTEL_SZ_MASK 0x18
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#define SH5_PTEL_SZ_4KB 0x00
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#define SH5_PTEL_SZ_64KB 0x08
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#define SH5_PTEL_SZ_1MB 0x10
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#define SH5_PTEL_SZ_512MB 0x18
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#define SH5_PTEL_PR_MASK 0x1e0
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#define SH5_PTEL_PR_R 0x040
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#define SH5_PTEL_PR_R_SHIFT 6
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#define SH5_PTEL_PR_X 0x080
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#define SH5_PTEL_PR_X_SHIFT 7
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#define SH5_PTEL_PR_W 0x100
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#define SH5_PTEL_PR_W_SHIFT 8
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#define SH5_PTEL_PR_U 0x200
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#define SH5_PTEL_PR_U_SHIFT 9
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#if SH5_NEFF_BITS == 32
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#define SH5_PTEL_PPN_MASK 0xfffff000UL
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#else
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#define SH5_PTEL_PPN_MASK 0xfffffffffffff000UL
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#endif
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#define SH5_PTE_PN_MASK_MOVI -4096 /* movi only accepts signed 16-bit #s */
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/*
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* Software bits stored in some low-order bits of an in-core PTEL
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*/
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#define SH5_PTEL_R 0x400 /* Set when the mapping is referenced */
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#define SH5_PTEL_M 0x800 /* Set when the mapping is modified */
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#define SH5_PTEL_RM_MASK 0xc00
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/*
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* The pmap_pteg_table consists of an array of Hash Buckets, called PTE Groups,
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* where each group is 8 PTEs in size. The number of groups is calculated
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* at boot time such that there is one group for every two NBPG-sized pages
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* of physical RAM.
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*/
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#define SH5_PTEG_SIZE 8
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typedef struct {
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volatile pte_t pte[SH5_PTEG_SIZE];
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} pteg_t;
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#endif /* _SH5_PTE_H */
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