189 lines
6.6 KiB
C
189 lines
6.6 KiB
C
/* $NetBSD: pccreg.h,v 1.6 2000/03/18 22:33:03 scw Exp $ */
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/*
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*
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* Copyright (c) 1995 Charles D. Cranor
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles D. Cranor.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* peripheral channel controller on mvme147
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*/
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#ifndef __MVME68K_PCCREG_H
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#define __MVME68K_PCCREG_H
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/*
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* Offsets to the MVME147's onboard device registers.
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* (Relative to the bus_space_tag_t passed in from 'mainbus')
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*/
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#define PCC_NVRAM_OFF 0x0000 /* offset of Mostek NVRAM/RTC chip */
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#define PCC_RTC_OFF 0x07f8 /* offset of clock registers NVRAM */
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#define PCC_REG_OFF 0x1000 /* offset of PCC chip registers */
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#define PCC_LE_OFF 0x1800 /* offset of LANCE ethernet chip */
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#define PCC_VME_OFF 0x2000 /* offset of VME chip */
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#define PCC_LPT_OFF 0x2800 /* offset of parallel port register */
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#define PCC_ZS0_OFF 0x3000 /* offset of first 8530 UART */
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#define PCC_ZS1_OFF 0x3800 /* offset of second 8530 UART */
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#define PCC_WDSC_OFF 0x4000 /* offset of 33c93 SCSI chip */
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/*
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* This is needed to figure out the boot device.
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* (The physical address of the boot device's registers are passed in
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* from the Boot ROM)
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*/
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#define PCC_PADDR(off) ((void *)(0xfffe0000u + (off)))
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/*
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* The PCC chip's own registers. These are 8-bits wide, unless
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* otherwise indicated.
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*/
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#define PCCREG_DMA_TABLE_ADDR 0x00 /* DMA table address (32-bit) */
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#define PCCREG_DMA_DATA_ADDR 0x04 /* DMA data address (32-bit) */
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#define PCCREG_DMA_BYTE_COUNT 0x08 /* DMA byte count (32-bit) */
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#define PCCREG_DMA_DATA_HOLD 0x0c /* DMA data hold register (32-bit) */
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#define PCCREG_TMR1_PRELOAD 0x10 /* Timer1 preload (16-bit) */
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#define PCCREG_TMR1_COUNT 0x12 /* Timer1 count (16-bit) */
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#define PCCREG_TMR2_PRELOAD 0x14 /* Timer2 preload (16-bit) */
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#define PCCREG_TMR2_COUNT 0x16 /* Timer2 count (16-bit) */
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#define PCCREG_TMR1_INTR_CTRL 0x18 /* Timer1 interrupt ctrl */
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#define PCCREG_TMR1_CONTROL 0x19 /* Timer1 ctrl reg */
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#define PCCREG_TMR2_INTR_CTRL 0x1a /* Timer2 interrupt ctrl */
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#define PCCREG_TMR2_CONTROL 0x1b /* Timer2 ctrl reg */
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#define PCCREG_ACFAIL_INTR_CTRL 0x1c /* ACFAIL intr reg */
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#define PCCREG_WDOG_INTR_CTRL 0x1d /* Watchdog intr reg */
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#define PCCREG_PRNT_INTR_CTRL 0x1e /* Printer intr reg */
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#define PCCREG_PRNT_CONTROL 0x1f /* Printer ctrl */
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#define PCCREG_DMA_INTR_CTRL 0x20 /* DMA interrupt control */
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#define PCCREG_DMA_CONTROL 0x21 /* DMA csr */
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#define PCCREG_BUSERR_INTR_CTRL 0x22 /* Bus error interrupt */
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#define PCCREG_DMA_STATUS 0x23 /* DMA status register */
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#define PCCREG_ABORT_INTR_CTRL 0x24 /* ABORT interrupt control reg */
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#define PCCREG_TABLE_ADDR_FC 0x25 /* Table address function code reg */
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#define PCCREG_SERIAL_INTR_CTRL 0x26 /* Serial interrupt reg */
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#define PCCREG_GENERAL_CONTROL 0x27 /* General control register */
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#define PCCREG_LANCE_INTR_CTRL 0x28 /* Ethernet interrupt */
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#define PCCREG_GENERAL_STATUS 0x29 /* General status */
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#define PCCREG_SCSI_INTR_CTRL 0x2a /* SCSI interrupt reg */
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#define PCCREG_SLAVE_BASE_ADDR 0x2b /* Slave base addr reg */
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#define PCCREG_SOFT1_INTR_CTRL 0x2c /* Software interrupt #1 cr */
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#define PCCREG_VECTOR_BASE 0x2d /* Interrupt base vector register */
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#define PCCREG_SOFT2_INTR_CTRL 0x2e /* Software interrupt #2 cr */
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#define PCCREG_REVISION 0x2f /* Revision level */
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#define PCCREG_SIZE 0x30
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/*
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* Convenience macros for reading the PCC chip's registers
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* through bus_space.
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*/
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#define pcc_reg_read(sc,r) \
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bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, (r))
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#define pcc_reg_read16(sc,r) \
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bus_space_read_2((sc)->sc_bust, (sc)->sc_bush, (r))
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#define pcc_reg_read32(sc,r) \
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bus_space_read_4((sc)->sc_bust, (sc)->sc_bush, (r))
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#define pcc_reg_write(sc,r,v) \
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bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, (r), (v))
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#define pcc_reg_write16(sc,r,v) \
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bus_space_write_2((sc)->sc_bust, (sc)->sc_bush, (r), (v))
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#define pcc_reg_write32(sc,r,v) \
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bus_space_write_4((sc)->sc_bust, (sc)->sc_bush, (r), (v))
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/*
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* we lock off our interrupt vector at 0x40.
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*/
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#define PCC_VECBASE 0x40
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#define PCC_NVEC 12
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/*
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* vectors we use
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*/
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#define PCCV_ACFAIL 0
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#define PCCV_BERR 1
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#define PCCV_ABORT 2
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#define PCCV_ZS 3
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#define PCCV_LE 4
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#define PCCV_SCSI 5
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#define PCCV_DMA 6
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#define PCCV_PRINTER 7
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#define PCCV_TIMER1 8
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#define PCCV_TIMER2 9
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#define PCCV_SOFT1 10
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#define PCCV_SOFT2 11
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/*
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* enable interrupt
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*/
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#define PCC_ICLEAR 0x80
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#define PCC_IENABLE 0x08
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/*
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* interrupt mask
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*/
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#define PCC_IMASK 0x7
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/*
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* clock/timer
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*/
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#define PCC_TIMERACK 0x80 /* ack intr */
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#define PCC_TIMER100HZ 63936 /* load value for 100Hz */
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#define PCC_TIMERCLEAR 0x0 /* reset and clear timer */
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#define PCC_TIMERSTOP 0x1 /* stop clock, but don't clear it */
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#define PCC_TIMERSTART 0x3 /* start timer */
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#define pcc_timer_hz2lim(hz) (65536 - (160000/(hz)))
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#define pcc_timer_us2lim(us) (65536 - (160000/(1000000/(us))))
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/*
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* serial control
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*/
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#define PCC_ZSEXTERN 0x10 /* let PCC supply vector */
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/*
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* abort switch
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*/
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#define PCC_ABORT_IEN 0x08 /* enable interrupt */
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#define PCC_ABORT_ABS 0x40 /* current state of switch */
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#define PCC_ABORT_ACK 0x80 /* interrupt active; write to ack */
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/*
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* general control register
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*/
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#define PCC_GENCR_IEN 0x10 /* global interrupt enable */
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#endif /* __MVME68K_PCCREG_H */
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