220 lines
6.1 KiB
C
220 lines
6.1 KiB
C
/* $NetBSD: intr.h,v 1.22 2001/07/16 16:53:00 thorpej Exp $ */
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/*-
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* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, and by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _I386_INTR_H_
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#define _I386_INTR_H_
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/* Interrupt priority `levels'. */
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#define IPL_NONE 9 /* nothing */
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#define IPL_SOFTCLOCK 8 /* timeouts */
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#define IPL_SOFTNET 7 /* protocol stacks */
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#define IPL_BIO 6 /* block I/O */
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#define IPL_NET 5 /* network */
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#define IPL_SOFTSERIAL 4 /* serial */
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#define IPL_TTY 3 /* terminal */
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#define IPL_IMP 3 /* memory allocation */
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#define IPL_AUDIO 2 /* audio */
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#define IPL_CLOCK 1 /* clock */
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#define IPL_HIGH 1 /* everything */
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#define IPL_SERIAL 0 /* serial */
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#define NIPL 10
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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/* Soft interrupt masks. */
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#define SIR_CLOCK 31
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#define SIR_NET 30
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#define SIR_SERIAL 29
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/* Hack for CLKF_INTR(). */
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#define IPL_TAGINTR 28
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#ifndef _LOCORE
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volatile int cpl, ipending, astpending;
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int imask[NIPL];
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void Xspllower __P((void));
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static __inline int splraise __P((int));
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static __inline void spllower __P((int));
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static __inline void softintr __P((int));
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/*
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* Add a mask to cpl, and return the old value of cpl.
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*/
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static __inline int
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splraise(ncpl)
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register int ncpl;
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{
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register int ocpl = cpl;
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cpl = ocpl | ncpl;
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return (ocpl);
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}
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/*
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* Restore a value to cpl (unmasking interrupts). If any unmasked
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* interrupts are pending, call Xspllower() to process them.
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*/
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static __inline void
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spllower(ncpl)
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register int ncpl;
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{
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cpl = ncpl;
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if (ipending & ~ncpl)
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Xspllower();
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}
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/*
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* Hardware interrupt masks
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*/
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#define splbio() splraise(imask[IPL_BIO])
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#define splnet() splraise(imask[IPL_NET])
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#define spltty() splraise(imask[IPL_TTY])
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#define splaudio() splraise(imask[IPL_AUDIO])
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#define splclock() splraise(imask[IPL_CLOCK])
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#define splstatclock() splclock()
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#define splserial() splraise(imask[IPL_SERIAL])
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#define spllpt() spltty()
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/*
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* Software interrupt masks
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*
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* NOTE: splsoftclock() is used by hardclock() to lower the priority from
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* clock to softclock before it calls softclock().
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*/
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#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
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#define splsoftclock() splraise(imask[IPL_SOFTCLOCK])
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#define splsoftnet() splraise(imask[IPL_SOFTNET])
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#define splsoftserial() splraise(imask[IPL_SOFTSERIAL])
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/*
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* Miscellaneous
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*/
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#define splvm() splraise(imask[IPL_IMP])
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#define splhigh() splraise(imask[IPL_HIGH])
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#define splsched() splhigh()
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#define spllock() splhigh()
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#define spl0() spllower(0)
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#define splx(x) spllower(x)
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/*
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* Software interrupt registration
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*
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* We hand-code this to ensure that it's atomic.
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*/
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static __inline void
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softintr(mask)
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register int mask;
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{
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__asm __volatile("orl %1, %0" : "=m"(ipending) : "ir" (1 << mask));
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}
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#define setsoftast() (astpending = 1)
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#define setsoftnet() softintr(SIR_NET)
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#endif /* !_LOCORE */
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/*
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* Generic software interrupt support.
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*/
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#define I386_SOFTINTR_SOFTCLOCK 0
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#define I386_SOFTINTR_SOFTNET 1
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#define I386_SOFTINTR_SOFTSERIAL 2
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#define I386_NSOFTINTR 3
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#ifndef _LOCORE
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#include <sys/queue.h>
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struct i386_soft_intrhand {
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TAILQ_ENTRY(i386_soft_intrhand)
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sih_q;
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struct i386_soft_intr *sih_intrhead;
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void (*sih_fn)(void *);
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void *sih_arg;
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int sih_pending;
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};
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struct i386_soft_intr {
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TAILQ_HEAD(, i386_soft_intrhand)
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softintr_q;
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int softintr_ssir;
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};
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#define i386_softintr_lock(si, s) \
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do { \
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/* XXX splhigh braindamage on i386 */ \
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(s) = splserial(); \
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} while (/*CONSTCOND*/ 0)
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#define i386_softintr_unlock(si, s) \
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do { \
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splx((s)); \
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} while (/*CONSTCOND*/ 0)
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void *softintr_establish(int, void (*)(void *), void *);
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void softintr_disestablish(void *);
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void softintr_init(void);
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void softintr_dispatch(int);
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#define softintr_schedule(arg) \
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do { \
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struct i386_soft_intrhand *__sih = (arg); \
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struct i386_soft_intr *__si = __sih->sih_intrhead; \
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int __s; \
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\
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i386_softintr_lock(__si, __s); \
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if (__sih->sih_pending == 0) { \
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TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
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__sih->sih_pending = 1; \
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softintr(__si->softintr_ssir); \
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} \
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i386_softintr_unlock(__si, __s); \
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} while (/*CONSTCOND*/ 0)
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#endif /* _LOCORE */
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#endif /* !_I386_INTR_H_ */
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