212 lines
5.8 KiB
C
212 lines
5.8 KiB
C
/* $NetBSD: wereg.h,v 1.2 2001/07/04 11:14:10 jdolecek Exp $ */
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/*
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* National Semiconductor DS8390 NIC register definitions.
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*
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* Copyright (C) 1993, David Greenman. This software may be used, modified,
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* copied, distributed, and sold, in both source and binary form provided that
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* the above copyright and these terms are retained. Under no circumstances is
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* the author responsible for the proper functioning of this software, nor does
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* the author assume any responsibility for damages incurred with its use.
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*/
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/*
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* Definitions for Western digital/SMC WD80x3 series ASIC
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*/
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/*
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* Memory Select Register (MSR)
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*/
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#define WE_MSR 0
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/* next three definitions for Toshiba */
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#define WE_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
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#define WE_MSR_BSY 0x04 /* gate array busy (R) */
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#define WE_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */
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#define WE_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
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#define WE_MSR_MENB 0x40 /* Memory enable */
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#define WE_MSR_RST 0x80 /* Reset board */
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/*
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* Interface Configuration Register (ICR)
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*/
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#define WE_ICR 1
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#define WE_ICR_16BIT 0x01 /* 16-bit interface */
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#define WE_ICR_OAR 0x02 /* select register (0=BIO 1=EAR) */
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#define WE_ICR_IR2 0x04 /* high order bit of encoded IRQ */
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#define WE_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
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#define WE_ICR_RLA 0x10 /* recall LAN address */
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#define WE_ICR_RX7 0x20 /* recall all but i/o and LAN address */
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#define WE_ICR_RIO 0x40 /* recall i/o address */
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#define WE_ICR_STO 0x80 /* store to non-volatile memory */
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#ifdef TOSH_ETHER
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#define WE_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
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#define WE_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
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0x02 = 16K, 0x01 = 8K */
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/* 64K can only be used if mem address
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above 1MB */
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/* IAR holds address A23-A16 (R/W) */
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#endif
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/*
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* IO Address Register (IAR)
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*/
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#define WE_IAR 2
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/*
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* EEROM Address Register
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*/
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#define WE_EAR 3
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/*
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* Interrupt Request Register (IRR)
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*/
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#define WE_IRR 4
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#define WE_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
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#define WE_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
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#define WE_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
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#define WE_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
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#define WE_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 2/9
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* 0 0 1 3
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* 0 1 0 5
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* 0 1 1 7
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* 1 0 0 10
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* 1 0 1 11
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* 1 1 0 15
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* 1 1 1 4
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*/
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#define WE_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
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#define WE_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
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#define WE_IRR_IEN 0x80 /* Interrupt enable */
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/*
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* LA Address Register (LAAR)
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*/
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#define WE_LAAR 5
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#define WE_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
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#define WE_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
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#define WE_LAAR_L16EN 0x40 /* enable 16-bit operation */
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#define WE_LAAR_M16EN 0x80 /* enable 16-bit memory access */
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/* i/o base offset to station address/card-ID PROM */
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#define WE_PROM 8
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/*
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* 83C790 specific registers
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*/
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/*
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* Hardware Support Register (HWR) ('790)
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*/
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#define WE790_HWR 4
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#define WE790_HWR_RST 0x10 /* hardware reset */
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#define WE790_HWR_LPRM 0x40 /* LAN PROM select */
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#define WE790_HWR_SWH 0x80 /* switch register set */
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/*
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* ICR790 Interrupt Control Register for the 83C790
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*/
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#define WE790_ICR 6
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#define WE790_ICR_EIL 0x01 /* enable interrupts */
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/*
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* REV/IOPA Revision / I/O Pipe register for the 83C79X
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*/
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#define WE790_REV 7
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#define WE790_REV_790 0x20
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#define WE790_REV_795 0x40
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/*
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* 79X RAM Address Register (RAR)
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* Enabled with SWH bit=1 in HWR register
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*/
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#define WE790_RAR 0x0b
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#define WE790_RAR_SZ8 0x00 /* 8k memory buffer */
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#define WE790_RAR_SZ16 0x10 /* 16k memory buffer */
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#define WE790_RAR_SZ32 0x20 /* 32k memory buffer */
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#define WE790_RAR_SZ64 0x30 /* 64k memory buffer */
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/*
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* General Control Register (GCR)
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* Enabled with SWH bit == 1 in HWR register
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*/
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#define WE790_GCR 0x0d
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#define WE790_GCR_LIT 0x01 /* on for UTP */
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#define WE790_GCR_GPOUT 0x02 /* if BNC is enabled */
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#define WE790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
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#define WE790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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#define WE790_GCR_ZWSEN 0x20 /* zero wait state enable */
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#define WE790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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* IR2 IR1 IR0 IRQ
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* 0 0 0 none
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* 0 0 1 9
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* 0 1 0 3
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* 0 1 1 5
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* 1 0 0 7
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* 1 0 1 10
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* 1 1 0 11
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* 1 1 1 15
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*/
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/* i/o base offset to CARD ID */
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#define WE_CARD_ID WE_PROM+6
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/* Board type codes in card ID */
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#define WE_TYPE_WD8003S 0x02
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#define WE_TYPE_WD8003E 0x03
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#define WE_TYPE_WD8013EBT 0x05
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#define WE_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
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#define WE_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
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#define WE_TYPE_TOSHIBA3 0x13 /* named PCETB */
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#define WE_TYPE_TOSHIBA4 0x14 /* named PCETC */
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#define WE_TYPE_WD8003W 0x24
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#define WE_TYPE_WD8003EB 0x25
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#define WE_TYPE_WD8013W 0x26
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#define WE_TYPE_WD8013EP 0x27
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#define WE_TYPE_WD8013WC 0x28
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#define WE_TYPE_WD8013EPC 0x29
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#define WE_TYPE_SMC8216T 0x2a
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#define WE_TYPE_SMC8216C 0x2b
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#define WE_TYPE_WD8013EBP 0x2c
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/* Bit definitions in card ID */
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#define WE_REV_MASK 0x1f /* Revision mask */
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#define WE_SOFTCONFIG 0x20 /* Soft config */
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#define WE_LARGERAM 0x40 /* Large RAM */
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#define WE_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
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/*
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* Checksum total. All 8 bytes in station address PROM will add up to this.
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*/
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#ifdef TOSH_ETHER
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#define WE_ROM_CHECKSUM_TOTAL 0xA5
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#else
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#define WE_ROM_CHECKSUM_TOTAL 0xFF
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#endif
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#define WE_NIC_OFFSET 0x10 /* I/O base offset to NIC */
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#define WE_ASIC_OFFSET 0 /* I/O base offset to ASIC */
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#define WE_NIC_NPORTS 16
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#define WE_ASIC_NPORTS 16
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#define WE_NPORTS (WE_NIC_NPORTS + WE_ASIC_NPORTS)
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#define WE_PAGE_OFFSET 0 /* page offset for NIC access to mem */
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