238 lines
7.4 KiB
C
238 lines
7.4 KiB
C
/* $NetBSD: gcscide.c,v 1.9 2011/04/04 20:37:51 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Juan Romero Pardines.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for the IDE Controller of the National Semiconductor/AMD
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* CS5535 Companion device. Available on systems with an AMD Geode GX2
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* CPU, for example the decTOP.
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*
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* Datasheet at:
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*
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* http://www.amd.com/files/connectivitysolutions/geode/geode_gx/31506_cs5535_databook.pdf
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gcscide.c,v 1.9 2011/04/04 20:37:51 dyoung Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <machine/cpufunc.h>
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/*
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* 6.4 - ATA-5 Controller Register Definitions.
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*/
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#define GCSCIDE_MSR_ATAC_BASE 0x51300000
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#define GCSCIDE_ATAC_GLD_MSR_CAP (GCSCIDE_MSR_ATAC_BASE + 0)
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#define GCSCIDE_ATAC_GLD_MSR_CONFIG (GCSCIDE_MSR_ATAC_BASE + 0x01)
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#define GCSCIDE_ATAC_GLD_MSR_SMI (GCSCIDE_MSR_ATAC_BASE + 0x02)
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#define GCSCIDE_ATAC_GLD_MSR_ERROR (GCSCIDE_MSR_ATAC_BASE + 0x03)
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#define GCSCIDE_ATAC_GLD_MSR_PM (GCSCIDE_MSR_ATAC_BASE + 0x04)
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#define GCSCIDE_ATAC_GLD_MSR_DIAG (GCSCIDE_MSR_ATAC_BASE + 0x05)
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#define GCSCIDE_ATAC_IO_BAR (GCSCIDE_MSR_ATAC_BASE + 0x08)
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#define GCSCIDE_ATAC_RESET (GCSCIDE_MSR_ATAC_BASE + 0x10)
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#define GCSCIDE_ATAC_CH0D0_PIO (GCSCIDE_MSR_ATAC_BASE + 0x20)
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#define GCSCIDE_ATAC_CH0D0_DMA (GCSCIDE_MSR_ATAC_BASE + 0x21)
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#define GCSCIDE_ATAC_CH0D1_PIO (GCSCIDE_MSR_ATAC_BASE + 0x22)
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#define GCSCIDE_ATAC_CH0D1_DMA (GCSCIDE_MSR_ATAC_BASE + 0x23)
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#define GCSCIDE_ATAC_PCI_ABRTERR (GCSCIDE_MSR_ATAC_BASE + 0x24)
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#define GCSCIDE_ATAC_BM0_CMD_PRIM 0x00
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#define GCSCIDE_ATAC_BM0_STS_PRIM 0x02
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#define GCSCIDE_ATAC_BM0_PRD 0x04
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/*
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* ATAC_CH0D0_DMA registers:
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*
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* PIO Format (bit 31): Format 1 allows independent control of command
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* and data per drive, while Format 0 selects the slowest speed
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* of the two drives.
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*/
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#define GCSCIDE_ATAC_PIO_FORMAT (1 << 31) /* PIO Mode Format 1 */
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/*
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* DMA_SEL (bit 20): sets Ultra DMA mode (if enabled) or Multi-word
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* DMA mode (if disabled).
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*/
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#define GCSCIDE_ATAC_DMA_SEL (1 << 20)
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static int gcscide_match(device_t, cfdata_t, void *);
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static void gcscide_attach(device_t, device_t, void *);
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static void gcscide_chip_map(struct pciide_softc *, const struct pci_attach_args *);
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static void gcscide_setup_channel(struct ata_channel *);
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/* PIO Format 1 settings */
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static const uint32_t gcscide_pio_timings[] = {
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0xf7f4f7f4, /* PIO Mode 0 */
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0x53f3f173, /* PIO Mode 1 */
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0x13f18141, /* PIO Mode 2 */
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0x51315131, /* PIO Mode 3 */
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0x11311131 /* PIO Mode 4 */
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};
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static const uint32_t gcscide_mdma_timings[] = {
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0x7f0ffff3, /* MDMA Mode 0 */
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0x7f035352, /* MDMA Mode 1 */
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0x7f024241 /* MDMA Mode 2 */
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};
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static const uint32_t gcscide_udma_timings[] = {
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0x7f7436a1, /* Ultra DMA Mode 0 */
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0x7f733481, /* Ultra DMA Mode 1 */
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0x7f723261, /* Ultra DMA Mode 2 */
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0x7f713161, /* Ultra DMA Mode 3 */
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0x7f703061 /* Ultra DMA Mode 4 */
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};
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CFATTACH_DECL_NEW(gcscide, sizeof(struct pciide_softc),
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gcscide_match, gcscide_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_gcscide_products[] = {
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{
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PCI_PRODUCT_NS_CS5535_IDE,
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0,
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"National Semiconductor/AMD CS5535 IDE Controller",
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gcscide_chip_map
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},
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{ 0, 0, NULL, NULL }
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};
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static int
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gcscide_match(device_t parent, cfdata_t cfdata, void *aux)
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{
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struct pci_attach_args *pa = (struct pci_attach_args *)aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
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PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE &&
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pciide_lookup_product(pa->pa_id, pciide_gcscide_products))
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return 2;
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return 0;
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}
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static void
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gcscide_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = device_private(self);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_gcscide_products));
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}
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static void
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gcscide_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
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{
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pcireg_t interface;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"bus-master DMA support present");
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_set_modes = gcscide_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
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interface = PCI_INTERFACE(pa->pa_class);
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wdc_allocate_regs(&sc->sc_wdcdev);
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if (pciide_chansetup(sc, 0, interface) == 0)
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return;
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pciide_mapchan(pa, &sc->pciide_channels[0], interface,
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pciide_pci_intr);
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}
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static void
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gcscide_setup_channel(struct ata_channel *chp)
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{
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct ata_drive_datas *drvp;
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uint64_t reg = 0;
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int drive, s;
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA);
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if (drvp->drive_flags & DRIVE_UDMA) {
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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/* Enable the Ultra DMA mode bit */
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reg |= GCSCIDE_ATAC_DMA_SEL;
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/* set the Ultra DMA mode */
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reg |= gcscide_udma_timings[drvp->UDMA_mode];
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA, reg);
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} else if (drvp->drive_flags & DRIVE_DMA) {
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/* Enable the Multi-word DMA bit */
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reg &= ~GCSCIDE_ATAC_DMA_SEL;
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/* set the Multi-word DMA mode */
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reg |= gcscide_mdma_timings[drvp->DMA_mode];
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA, reg);
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}
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/* Always use PIO Format 1. */
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA :
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GCSCIDE_ATAC_CH0D0_DMA, reg | GCSCIDE_ATAC_PIO_FORMAT);
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/* Set PIO mode */
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wrmsr(drive ? GCSCIDE_ATAC_CH0D1_PIO : GCSCIDE_ATAC_CH0D0_PIO,
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gcscide_pio_timings[drvp->PIO_mode]);
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}
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}
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