276 lines
8.5 KiB
C
276 lines
8.5 KiB
C
/* $NetBSD: optiide.c,v 1.16 2008/03/18 20:46:37 cube Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: optiide.c,v 1.16 2008/03/18 20:46:37 cube Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_opti_reg.h>
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static void opti_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void opti_setup_channel(struct ata_channel*);
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static int optiide_match(device_t, cfdata_t, void *);
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static void optiide_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(optiide, sizeof(struct pciide_softc),
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optiide_match, optiide_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_opti_products[] = {
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{ PCI_PRODUCT_OPTI_82C621,
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0,
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"OPTi 82c621 PCI IDE controller",
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opti_chip_map,
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},
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{ PCI_PRODUCT_OPTI_82C568,
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0,
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"OPTi 82c568 (82c621 compatible) PCI IDE controller",
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opti_chip_map,
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},
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{ PCI_PRODUCT_OPTI_82D568,
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0,
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"OPTi 82d568 (82c621 compatible) PCI IDE controller",
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opti_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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optiide_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI &&
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PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
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if (pciide_lookup_product(pa->pa_id, pciide_opti_products))
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return (2);
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}
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return (0);
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}
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static void
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optiide_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = device_private(self);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_opti_products));
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}
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static void
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opti_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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bus_size_t cmdsize, ctlsize;
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pcireg_t interface;
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u_int8_t init_ctrl;
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int channel;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"bus-master DMA support present");
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/*
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* XXXSCW:
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* There seem to be a couple of buggy revisions/implementations
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* of the OPTi pciide chipset. This kludge seems to fix one of
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* the reported problems (PR/11644) but still fails for the
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* other (PR/13151), although the latter may be due to other
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* issues too...
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*/
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if (PCI_REVISION(pa->pa_class) <= 0x12) {
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aprint_verbose(" but disabled due to chip rev. <= 0x12");
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sc->sc_dma_ok = 0;
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} else
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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}
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sc->sc_wdcdev.sc_atac.atac_set_modes = opti_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag,
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OPTI_REG_INIT_CONTROL);
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interface = PCI_INTERFACE(pa->pa_class);
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if (channel == 1 &&
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(init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) {
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aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"%s channel ignored (disabled)\n", cp->name);
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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continue;
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}
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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pciide_pci_intr);
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}
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}
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static void
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opti_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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int drive, spd, s;
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int mode[2];
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u_int8_t rv, mr;
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/*
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* The `Delay' and `Address Setup Time' fields of the
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* Miscellaneous Register are always zero initially.
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*/
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mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK;
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mr &= ~(OPTI_MISC_DELAY_MASK |
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OPTI_MISC_ADDR_SETUP_MASK |
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OPTI_MISC_INDEX_MASK);
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/* Prime the control register before setting timing values */
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opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE);
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/* Determine the clockrate of the PCIbus the chip is attached to */
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spd = (int) opti_read_config(chp, OPTI_REG_STRAP);
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spd &= OPTI_STRAP_PCI_SPEED_MASK;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0) {
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mode[drive] = -1;
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continue;
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}
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if ((drvp->drive_flags & DRIVE_DMA)) {
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/*
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed
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*/
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if (drvp->PIO_mode > (drvp->DMA_mode + 2))
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drvp->PIO_mode = drvp->DMA_mode + 2;
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if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
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drvp->DMA_mode = (drvp->PIO_mode > 2) ?
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drvp->PIO_mode - 2 : 0;
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if (drvp->DMA_mode == 0)
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drvp->PIO_mode = 0;
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mode[drive] = drvp->DMA_mode + 5;
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} else
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mode[drive] = drvp->PIO_mode;
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if (drive && mode[0] >= 0 &&
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(opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) {
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/*
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* Can't have two drives using different values
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* for `Address Setup Time'.
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* Slow down the faster drive to compensate.
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*/
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int d = (opti_tim_as[spd][mode[0]] >
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opti_tim_as[spd][mode[1]]) ? 0 : 1;
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mode[d] = mode[1-d];
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chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode;
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chp->ch_drive[d].DMA_mode = 0;
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s = splbio();
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chp->ch_drive[d].drive_flags &= ~DRIVE_DMA;
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splx(s);
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}
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}
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for (drive = 0; drive < 2; drive++) {
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int m;
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if ((m = mode[drive]) < 0)
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continue;
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/* Set the Address Setup Time and select appropriate index */
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rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT;
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rv |= OPTI_MISC_INDEX(drive);
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opti_write_config(chp, OPTI_REG_MISC, mr | rv);
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/* Set the pulse width and recovery timing parameters */
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rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT;
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rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT;
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opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv);
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opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv);
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/* Set the Enhanced Mode register appropriately */
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rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE);
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rv &= ~OPTI_ENH_MODE_MASK(chp->ch_channel, drive);
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rv |= OPTI_ENH_MODE(chp->ch_channel, drive, opti_tim_em[m]);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv);
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}
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/* Finally, enable the timings */
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opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE);
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}
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