181 lines
6.2 KiB
C
181 lines
6.2 KiB
C
/* $NetBSD: nslm7xvar.h,v 1.17 2005/12/11 12:21:28 christos Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Bill Squier.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_ISA_NSLM7XVAR_H_
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#define _DEV_ISA_NSLM7XVAR_H_
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/* ctl registers */
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#define LMC_ADDR 0x05
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#define LMC_DATA 0x06
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/* data registers */
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#define LMD_SENSORBASE 0x20 /* Sensors occupy 0x20 -- 0x2a */
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#define LMD_CONFIG 0x40 /* Configuration */
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#define LMD_ISR1 0x41 /* Interrupt Status 1 */
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#define LMD_ISR2 0x42 /* Interrupt Status 2 */
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#define LMD_SMI1 0x43 /* SMI Mask 1 */
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#define LMD_SMI2 0x44 /* SMI Mask 2 */
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#define LMD_NMI1 0x45 /* NMI Mask 1 */
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#define LMD_NMI2 0x46 /* NMI Mask 2 */
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#define LMD_VIDFAN 0x47 /* VID/Fan Divisor */
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#define LMD_SBUSADDR 0x48 /* Serial Bus Address */
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#define LMD_CHIPID 0x49 /* Chip Reset/ID */
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/* misc constants */
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#define LM_NUM_SENSORS 11
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#define LM_ID_LM78 0x00
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#define LM_ID_LM78J 0x40
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#define LM_ID_LM79 0xC0
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#define LM_ID_LM81 0x80
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#define LM_ID_MASK 0xFE
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/*
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* additional registers for the Winbond chips:
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* WB83781D: mostly lm7x compatible; extra temp sensors in bank1 & 2
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* WB83782D & WB83627HF: voltage sensors needs different handling, more FAN
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* dividers; mode voltage sensors, more temp sensors.
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*/
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#define WB_T23ADDR 0x4A /* temp sens 2/3 I2C addr */
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#define WB_PIN 0x4B /* pin & fan3 divider */
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#define WB_BANKSEL 0x4E /* banck select register */
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#define WB_BANKSEL_B0 0x00 /* select bank 0 */
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#define WB_BANKSEL_B1 0x01 /* select bank 1 */
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#define WB_BANKSEL_B2 0x02 /* select bank 2 */
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#define WB_BANKSEL_B3 0x03 /* select bank 3 */
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#define WB_BANKSEL_B4 0x04 /* select bank 4 */
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#define WB_BANKSEL_B5 0x05 /* select bank 5 */
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#define WB_BANKSEL_HBAC 0x80 /* hight byte access */
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#define WB_VENDID 0x4F /* vendor ID register */
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#define WB_VENDID_WINBOND 0x5CA3
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/* Bank0 regs */
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#define WB_BANK0_CHIPID 0x58
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#define WB_CHIPID_83781 0x10
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#define WB_CHIPID_83781_2 0x11
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#define WB_CHIPID_83782 0x30
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#define WB_CHIPID_83627 0x21
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#define WB_CHIPID_83627THF 0x90
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#define WB_CHIPID_83697 0x60
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#define WB_BANK0_FANBAT 0x5D
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/* Bank1 regs */
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#define WB_BANK1_T2H 0x50
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#define WB_BANK1_T2L 0x51
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/* Bank2 regs */
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#define WB_BANK2_T3H 0x50
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#define WB_BANK2_T3L 0x51
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/* Bank4 regs 83782/83627 only */
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#define WB_BANK4_T1OFF 0x54
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#define WB_BANK4_T2OFF 0x55
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#define WB_BANK4_T3OFF 0x56
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/* Bank5 regs 83782/83627 only */
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#define WB_BANK5_5VSB 0x50
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#define WB_BANK5_VBAT 0x51
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#define WB83781_NUM_SENSORS 13
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#define WB83697_NUM_SENSORS 14
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#define WB_NUM_SENSORS 15
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/*
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* registers for the environment controller built into
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* the IT8705F super-i/o chip
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*/
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#define ITEC_FANDIV 0x0b /* fan divisor */
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#define ITEC_FAN1 0x0d /* fan1 tachometer */
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#define ITEC_FAN2 0x0e /* fan2 tachometer */
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#define ITEC_FAN3 0x0f /* fan3 tachometer */
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#define ITEC_VIN0 0x20 /* VIN0 voltage */
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#define ITEC_VIN1 0x21 /* VIN1 voltage */
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#define ITEC_VIN2 0x22 /* VIN2 voltage */
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#define ITEC_VIN3 0x23 /* VIN3 voltage */
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#define ITEC_VIN4 0x24 /* VIN4 voltage */
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#define ITEC_VIN5 0x25 /* VIN5 voltage */
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#define ITEC_VIN6 0x26 /* VIN6 voltage */
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#define ITEC_VIN7 0x27 /* VIN7 voltage */
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#define ITEC_VBAT 0x28 /* VBAT voltage */
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#define ITEC_TEMP1 0x29 /* TMPIN1 temperature */
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#define ITEC_TEMP2 0x30 /* TMPIN1 temperature */
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#define ITEC_TEMP3 0x31 /* TMPIN1 temperature */
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#define ITEC_RES48 0x48 /* reserved, used for probing the chip */
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#define ITEC_RES52 0x52 /* reserved, used for probing the chip */
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#define ITEC_VENDID 0x58 /* vendor ID register */
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#define ITEC_COREID 0x5b /* core ID register, only 8712F */
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/*
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* misc values
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*/
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#define ITEC_VENDID_ITE 0x90 /* iTE vendor ID */
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#define ITEC_COREID_ITE 0x12 /* iTE core ID */
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#define ITEC_RES48_DEFAULT 0x2d
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#define ITEC_RES52_DEFAULT 0x7f
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#define ITEC_NUM_SENSORS 15
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#define ITEC_VREF 4096 /* VREF in mV */
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struct lm_softc {
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struct device sc_dev;
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int lm_iobase;
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bus_space_tag_t lm_iot;
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bus_space_handle_t lm_ioh;
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int sc_flags;
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struct timeval lastread; /* only allow reads every 1.5 seconds */
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struct envsys_tre_data sensors[WB_NUM_SENSORS];
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struct envsys_basic_info info[WB_NUM_SENSORS];
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u_int numsensors;
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void (*refresh_sensor_data)(struct lm_softc *);
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int (*lm_banksel)(struct lm_softc *, int);
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u_int8_t (*lm_readreg)(struct lm_softc *, int);
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void (*lm_writereg)(struct lm_softc *, int, int);
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struct sysmon_envsys sc_sysmon;
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};
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void lm_attach(struct lm_softc *);
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int lm_probe(bus_space_tag_t, bus_space_handle_t);
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#endif /* _DEV_ISA_NSLM7XVAR_H_ */
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