289 lines
8.1 KiB
C
289 lines
8.1 KiB
C
/* $NetBSD: imc.c,v 1.16 2004/01/18 13:11:18 sekiya Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.16 2004/01/18 13:11:18 sekiya Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/locore.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/machtype.h>
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#include <machine/sysconf.h>
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#include <sgimips/dev/imcreg.h>
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#include "locators.h"
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struct imc_softc {
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struct device sc_dev;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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int eisa_present : 1;
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};
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static int imc_match(struct device *, struct cfdata *, void *);
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static void imc_attach(struct device *, struct device *, void *);
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static int imc_print(void *, const char *);
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void imc_bus_reset(void);
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void imc_bus_error(void);
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void imc_watchdog_reset(void);
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void imc_watchdog_disable(void);
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void imc_watchdog_enable(void);
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CFATTACH_DECL(imc, sizeof(struct imc_softc),
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imc_match, imc_attach, NULL, NULL);
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struct imc_attach_args {
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const char* iaa_name;
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bus_space_tag_t iaa_st;
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bus_space_handle_t iaa_sh;
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/* ? */
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long iaa_offset;
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int iaa_intr;
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#if 0
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int iaa_stride;
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#endif
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};
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struct imc_softc isc;
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static int
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imc_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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if ( (mach_type == MACH_SGI_IP22) || (mach_type == MACH_SGI_IP20) )
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return (1);
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return (0);
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}
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static void
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imc_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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u_int32_t reg;
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struct imc_attach_args iaa;
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struct mainbus_attach_args *ma = aux;
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u_int32_t sysid;
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isc.iot = SGIMIPS_BUS_SPACE_HPC;
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if (bus_space_map(isc.iot, ma->ma_addr, 0,
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BUS_SPACE_MAP_LINEAR, &isc.ioh))
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panic("imc_attach: could not allocate memory\n");
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platform.bus_reset = imc_bus_reset;
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platform.watchdog_reset = imc_watchdog_reset;
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platform.watchdog_disable = imc_watchdog_disable;
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platform.watchdog_enable = imc_watchdog_enable;
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sysid = bus_space_read_4(isc.iot, isc.ioh, IMC_SYSID);
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/* EISA present bit is on even on Indys, so don't trust it! */
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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isc.eisa_present = (sysid & IMC_SYSID_HAVEISA);
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else
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isc.eisa_present = 0;
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printf(": revision %d", (sysid & IMC_SYSID_REVMASK));
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if (isc.eisa_present)
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printf(", EISA bus present");
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printf("\n");
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/* Clear CPU/GIO error status registers to clear any leftover bits. */
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT, 0);
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bus_space_write_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT, 0);
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/*
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* Enable parity reporting on GIO/main memory transactions.
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* Disable parity checking on CPU bus transactions (as turning
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* it on seems to cause spurious bus errors), but enable parity
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* checking on CPU reads from main memory (note that this bit
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* has the opposite sense... Turning it on turns the checks off!).
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* Finally, turn on interrupt writes to the CPU from the MC.
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*/
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;
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reg |= (IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR | IMC_CPUCTRL0_INTENA);
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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/* Setup the MC write buffer depth */
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL1);
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reg = (reg & ~IMC_CPUCTRL1_MCHWMSK) | 13;
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if (mach_type == MACH_SGI_IP20)
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reg = (reg & ~IMC_CPUCTRL1_HPCLITTLE) | IMC_CPUCTRL1_HPCFX;
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL1, reg);
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/*
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* Set GIO64 arbitrator configuration register:
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*
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* Preserve PROM-set graphics-related bits, as they seem to depend
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* on the graphics variant present and I'm not sure how to figure
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* that out or 100% sure what the correct settings are for each.
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*/
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);
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reg &= (IMC_GIO64ARB_GRX64 | IMC_GIO64ARB_GRXRT | IMC_GIO64ARB_GRXMST);
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/* GIO64 invariant for all IP22 platforms: one GIO bus, HPC1 @ 64 */
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reg |= IMC_GIO64ARB_ONEGIO | IMC_GIO64ARB_HPC64;
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/* Rest of settings are machine/board dependant */
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if (mach_type == MACH_SGI_IP20)
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{
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reg |= (IMC_GIO64ARB_ONEGIO |
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IMC_GIO64ARB_EXP1RT | IMC_GIO64ARB_EXP0RT);
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reg &= ~(IMC_GIO64ARB_HPC64 |
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IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EISA64 |
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IMC_GIO64ARB_EXP064 | IMC_GIO64ARB_EXP164 |
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IMC_GIO64ARB_EXP0PIPE | IMC_GIO64ARB_EXP1PIPE |
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IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);
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/* XXX second ethernet adapter */
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reg |= IMC_GIO64ARB_EXP0MST;
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}
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else
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{
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switch (mach_subtype) {
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case MACH_SGI_IP22_GUINESS:
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/* EISA can bus-master, is 64-bit */
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reg |= (IMC_GIO64ARB_EISAMST | IMC_GIO64ARB_EISA64);
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break;
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case MACH_SGI_IP22_FULLHOUSE:
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/*
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* All Fullhouse boards have a 64-bit HPC2 and pipelined
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* EXP0 slot.
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*/
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reg |= (IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EXP0PIPE);
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if (mach_boardrev < 2) {
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/* EXP0 realtime, EXP1 can master */
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reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1MST);
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} else {
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/* EXP1 pipelined as well, EISA masters */
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reg |= (IMC_GIO64ARB_EXP1PIPE | IMC_GIO64ARB_EISAMST);
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}
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break;
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}
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}
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bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);
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if (isc.eisa_present) {
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#if notyet
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memset(&iaa, 0, sizeof(iaa));
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iaa.iaa_name = "eisa";
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(void)config_found(self, (void*)&iaa, imc_print);
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#endif
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}
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memset(&iaa, 0, sizeof(iaa));
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iaa.iaa_name = "gio";
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(void)config_found(self, (void*)&iaa, imc_print);
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imc_watchdog_enable();
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}
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static int
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imc_print(aux, name)
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void *aux;
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const char *name;
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{
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struct imc_attach_args* iaa = aux;
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if (name)
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aprint_normal("%s at %s", iaa->iaa_name, name);
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return UNCONF;
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}
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void
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imc_bus_reset(void)
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{
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT, 0);
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bus_space_write_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT, 0);
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}
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void
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imc_bus_error(void)
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{
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printf("bus error: cpu_stat %08x addr %08x, gio_stat %08x addr %08x\n",
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bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT),
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bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRADDR),
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bus_space_read_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT),
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bus_space_read_4(isc.iot, isc.ioh, IMC_GIO_ERRADDR) );
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imc_bus_reset();
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}
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void
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imc_watchdog_reset(void)
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{
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bus_space_write_4(isc.iot, isc.ioh, IMC_WDOG, 0);
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}
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void
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imc_watchdog_disable(void)
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{
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u_int32_t reg;
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bus_space_write_4(isc.iot, isc.ioh, IMC_WDOG, 0);
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg &= ~(IMC_CPUCTRL0_WDOG);
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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}
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void
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imc_watchdog_enable(void)
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{
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u_int32_t reg;
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/* enable watchdog and clear it */
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg |= IMC_CPUCTRL0_WDOG;
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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imc_watchdog_reset();
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}
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