417 lines
12 KiB
C
417 lines
12 KiB
C
/* $NetBSD: ugvar.h,v 1.3 2007/01/20 18:32:41 xtraeme Exp $ */
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/*
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* Copyright (c) 2007 Mihai Chelaru <kefren@netbsd.ro>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_ISA_UGVAR_H
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#define _DEV_ISA_UGVAR_H
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#define UG_DRV_VERSION 1000
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/*
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* Abit uGuru (first version)
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*/
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#define UG_DELAY_CYCLES 5000
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#define UG_NUM_SENSORS 19
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#define UG_MAX_SENSORS 32
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/* Data and Cmd offsets - Base is ussualy 0xE0 */
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#define UG_CMD 0
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#define UG_DATA 4
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/* Temp and Voltage Sensors */
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#define UG_CPUTEMP 0x2100
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#define UG_SYSTEMP 0x2101
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#define UG_HTV 0x2102
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#define UG_VCORE 0x2103
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#define UG_DDRVDD 0x2104
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#define UG_3V3 0x2105
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#define UG_5V 0x2106
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#define UG_NBVDD 0x2108
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#define UG_AGP 0x2109
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#define UG_DDRVTT 0x210A
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#define UG_5VSB 0x210B
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#define UG_3VDUAL 0x210D
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#define UG_SBVDD 0x210E
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#define UG_PWMTEMP 0x210F
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/* Fans */
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#define UG_CPUFAN 0x2600
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#define UG_NBFAN 0x2601
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#define UG_SYSFAN 0x2602
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#define UG_AUXFAN1 0x2603
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#define UG_AUXFAN2 0x2604
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/* RFacts */
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#define UG_RFACT 1000
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#define UG_RFACT3 3490 * UG_RFACT / 255
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#define UG_RFACT4 4360 * UG_RFACT / 255
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#define UG_RFACT6 6250 * UG_RFACT / 255
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#define UG_RFACT_FAN 15300/255
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/*
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* sc->sensors sub-intervals for each unit type.
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*/
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static const struct envsys_range ug_ranges[] = {
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{ 0, 2, ENVSYS_STEMP },
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{ 14, 18, ENVSYS_SFANRPM },
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{ 1, 0, ENVSYS_SVOLTS_AC }, /* None */
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{ 3, 13, ENVSYS_SVOLTS_DC },
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{ 1, 0, ENVSYS_SOHMS }, /* None */
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{ 1, 0, ENVSYS_SWATTS }, /* None */
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{ 1, 0, ENVSYS_SAMPS } /* None */
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};
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struct ug_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct sysmon_envsys sc_sysmon;
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envsys_tre_data_t sc_data[UG_MAX_SENSORS];
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envsys_basic_info_t sc_info[UG_MAX_SENSORS];
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uint8_t version;
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void *mbsens;
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};
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/*
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* Abit uGuru2 or uGuru 2005 settings
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*/
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/* Sensor banks */
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#define UG2_SETTINGS_BANK 0x01
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#define UG2_SENSORS_BANK 0x08
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#define UG2_MISC_BANK 0x09
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/* Sensor offsets */
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#define UG2_ALARMS_OFFSET 0x1E
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#define UG2_SETTINGS_OFFSET 0x24
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#define UG2_VALUES_OFFSET 0x80
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/* Misc Sensor */
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#define UG2_BOARD_ID 0x0A
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/* sensor types */
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#define UG2_VOLTAGE_SENSOR 0
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#define UG2_TEMP_SENSOR 1
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#define UG2_FAN_SENSOR 2
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/* uGuru status flags */
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#define UG2_STATUS_READY_FOR_READ 0x01
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#define UG2_STATUS_BUSY 0x02
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/* No more than 32 sensors */
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#define UG2_MAX_NO_SENSORS 32
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struct ug2_sensor_info {
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const char *name;
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int port;
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int type;
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int multiplier;
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int divisor;
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int offset;
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};
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struct ug2_motherboard_info {
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uint16_t id;
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const char *name;
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struct ug2_sensor_info sensors[UG2_MAX_NO_SENSORS + 1];
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};
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/* Unknown board should be the last. Now is 0x0016 */
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#define UG_MAX_MSB_BOARD 0x00
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#define UG_MAX_LSB_BOARD 0x16
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#define UG_MIN_LSB_BOARD 0x0c
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/*
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* Imported from linux driver
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*/
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struct ug2_motherboard_info ug2_mb[] = {
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{ 0x000C, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS FAN", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x000D, "Abit AW8", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM1", 26, 1, 1, 1, 0 },
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{ "PWM2", 27, 1, 1, 1, 0 },
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{ "PWM3", 28, 1, 1, 1, 0 },
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{ "PWM4", 29, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "AUX2 Fan", 36, 2, 60, 1, 0 },
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{ "AUX3 Fan", 37, 2, 60, 1, 0 },
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{ "AUX4 Fan", 38, 2, 60, 1, 0 },
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{ "AUX5 Fan", 39, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x000E, "Abit AL8", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x000F, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0010, "Abit NI8 SLI GR", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "NB 1.4V", 4, 0, 10, 1, 0 },
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{ "SB 1.5V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "SYS", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "OTES1 Fan", 36, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0011, "Abit AT8 32X", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 20, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
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{ "NB 1.8V", 4, 0, 10, 1, 0 },
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{ "NB 1.8V Dual", 5, 0, 10, 1, 0 },
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{ "HTV 1.2", 3, 0, 10, 1, 0 },
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{ "PCIE 1.2V", 12, 0, 10, 1, 0 },
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{ "NB 1.2V", 13, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "NB", 25, 1, 1, 1, 0 },
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{ "System", 26, 1, 1, 1, 0 },
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{ "PWM", 27, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "AUX2 Fan", 36, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0012, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 20, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "HyperTransport", 3, 0, 10, 1, 0 },
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{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
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{ "NB", 4, 0, 10, 1, 0 },
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{ "SB", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "SYS", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 36, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0013, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM1", 26, 1, 1, 1, 0 },
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{ "PWM2", 27, 1, 1, 1, 0 },
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{ "PWM3", 28, 1, 1, 1, 0 },
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{ "PWM4", 29, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 35, 2, 60, 1, 0 },
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{ "AUX2 Fan", 36, 2, 60, 1, 0 },
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{ "AUX3 Fan", 37, 2, 60, 1, 0 },
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{ "AUX4 Fan", 38, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0014, "Abit AB9 Pro", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 10, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
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{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
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{ "MCH 2.5V", 5, 0, 20, 1, 0 },
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{ "ICH 1.05V", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "System", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ NULL, 0, 0, 0, 0, 0 } }
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},
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{ 0x0015, "unknown. Please send-pr(1)", {
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{ "CPU Core", 0, 0, 10, 1, 0 },
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{ "DDR", 1, 0, 20, 1, 0 },
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{ "DDR VTT", 2, 0, 10, 1, 0 },
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{ "HyperTransport", 3, 0, 10, 1, 0 },
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{ "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
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{ "NB", 4, 0, 10, 1, 0 },
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{ "SB", 6, 0, 10, 1, 0 },
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{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
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{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
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{ "ATX +5V", 9, 0, 30, 1, 0 },
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{ "+3.3V", 10, 0, 20, 1, 0 },
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{ "5VSB", 11, 0, 30, 1, 0 },
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{ "CPU", 24, 1, 1, 1, 0 },
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{ "SYS", 25, 1, 1, 1, 0 },
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{ "PWM", 26, 1, 1, 1, 0 },
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{ "CPU Fan", 32, 2, 60, 1, 0 },
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{ "NB Fan", 33, 2, 60, 1, 0 },
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{ "SYS Fan", 34, 2, 60, 1, 0 },
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{ "AUX1 Fan", 33, 2, 60, 1, 0 },
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{ "AUX2 Fan", 35, 2, 60, 1, 0 },
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{ "AUX3 Fan", 36, 2, 60, 1, 0 },
|
|
{ NULL, 0, 0, 0, 0, 0 } }
|
|
},
|
|
{ 0x0016, "generic", {
|
|
{ "CPU Core", 0, 0, 10, 1, 0 },
|
|
{ "DDR", 1, 0, 20, 1, 0 },
|
|
{ "DDR VTT", 2, 0, 10, 1, 0 },
|
|
{ "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
|
|
{ "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
|
|
{ "MCH 2.5V", 5, 0, 20, 1, 0 },
|
|
{ "ICH 1.05V", 6, 0, 10, 1, 0 },
|
|
{ "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
|
|
{ "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
|
|
{ "ATX +5V", 9, 0, 30, 1, 0 },
|
|
{ "+3.3V", 10, 0, 20, 1, 0 },
|
|
{ "5VSB", 11, 0, 30, 1, 0 },
|
|
{ "CPU", 24, 1, 1, 1, 0 },
|
|
{ "System", 25, 1, 1, 1, 0 },
|
|
{ "PWM", 26, 1, 1, 1, 0 },
|
|
{ "CPU Fan", 32, 2, 60, 1, 0 },
|
|
{ "NB Fan", 33, 2, 60, 1, 0 },
|
|
{ "SYS FAN", 34, 2, 60, 1, 0 },
|
|
{ "AUX1 Fan", 35, 2, 60, 1, 0 },
|
|
{ NULL, 0, 0, 0, 0, 0 } }
|
|
},
|
|
{ 0x0000, NULL, { { NULL, 0, 0, 0, 0, 0 } } }
|
|
};
|
|
|
|
#endif /* _DEV_ISA_UGVAR_H_ */
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