389 lines
11 KiB
C
389 lines
11 KiB
C
/* $NetBSD: upc.c,v 1.12 2005/12/11 12:21:29 christos Exp $ */
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/*-
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* Copyright (c) 2000, 2003 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* upc - driver for C&T Universal Peripheral Controllers
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*
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* Supports:
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* 82C710 Universal Peripheral Controller
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* 82C711 Universal Peripheral Controller II
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* 82C721 Universal Peripheral Controller III (untested)
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*
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* The 82C710 is substantially different from its successors.
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* Functions that just handle the 82C710 are named upc1_*, which those
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* that handle the 82C711 and 82C721 are named upc2_*.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: upc.c,v 1.12 2005/12/11 12:21:29 christos Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <dev/ata/atavar.h> /* XXX needed by wdcvar.h */
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#include <dev/ic/comreg.h>
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#include <dev/ic/lptreg.h>
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#include <dev/ic/lptvar.h>
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#include <dev/ic/wdcreg.h>
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#include <dev/ic/wdcvar.h>
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#include <dev/ic/upcreg.h>
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#include <dev/ic/upcvar.h>
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#include "locators.h"
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/* Conventional port to use for 82C710 configuration */
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#define UPC1_PORT_CRI 0x390
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#define UPC1_PORT_CAP (UPC1_PORT_CRI + 1)
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static int upc1_probe(struct upc_softc *);
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static void upc1_attach(struct upc_softc *);
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static void upc2_attach(struct upc_softc *);
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static void upc_found(struct upc_softc *, char const *, int, int,
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struct upc_irqhandle *);
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static void upc_found2(struct upc_softc *, char const *, int, int, int, int,
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struct upc_irqhandle *);
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static int upc_print(void *, char const *);
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static int upc2_com3_addr(int);
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static int upc2_com4_addr(int);
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void
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upc_attach(struct upc_softc *sc)
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{
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if (upc1_probe(sc))
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upc1_attach(sc);
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else
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upc2_attach(sc);
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}
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static int
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upc1_probe(struct upc_softc *sc)
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{
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return upc1_read_config(sc, UPC1_CFGADDR_CONFBASE) ==
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UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT;
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}
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static void
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upc1_attach(struct upc_softc *sc)
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{
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u_int8_t cr[16];
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int i;
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aprint_normal(": 82C710\n");
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/* Dump configuration */
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for (i = 0; i < 16; i++)
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cr[i] = upc1_read_config(sc, i);
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aprint_verbose("%s: config state", sc->sc_dev.dv_xname);
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for (i = 0; i < 16; i++)
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aprint_verbose(" %02x", cr[i]);
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aprint_verbose("\n");
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/* FDC */
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if (cr[UPC1_CFGADDR_CRC] & UPC1_CRC_FDCEN)
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upc_found(sc, "fdc", UPC_PORT_FDCBASE, 2, &sc->sc_fintr);
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/* IDE */
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if (cr[UPC1_CFGADDR_CRC] & UPC1_CRC_IDEEN)
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upc_found2(sc, "wdc", UPC_PORT_IDECMDBASE, 8,
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UPC_PORT_IDECTLBASE, 2, &sc->sc_wintr);
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/* Parallel */
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if (cr[UPC1_CFGADDR_CR0] & UPC1_CR0_PEN)
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upc_found(sc, "lpt",
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cr[UPC1_CFGADDR_PARBASE] << UPC1_PARBASE_SHIFT,
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LPT_NPORTS, &sc->sc_pintr);
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/* UART */
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if (cr[UPC1_CFGADDR_CR0] & UPC1_CR0_SEN)
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upc_found(sc, "com",
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cr[UPC1_CFGADDR_UARTBASE] << UPC1_UARTBASE_SHIFT,
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COM_NPORTS, &sc->sc_irq4);
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/* Mouse */
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/* XXX not yet supported */
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}
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static void
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upc2_attach(struct upc_softc *sc)
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{
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u_int8_t cr[5];
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int i;
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aprint_normal(": 82C711/82C721");
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/* Dump configuration */
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for (i = 0; i < 5; i++)
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cr[i] = upc2_read_config(sc, i);
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aprint_verbose(", config state %02x %02x %02x %02x %02x",
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cr[0], cr[1], cr[2], cr[3], cr[4]);
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aprint_normal("\n");
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/* "Find" the attached devices */
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/* FDC */
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if (cr[0] & UPC2_CR0_FDC_ENABLE)
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upc_found(sc, "fdc", UPC_PORT_FDCBASE, 2, &sc->sc_fintr);
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/* IDE */
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if (cr[0] & UPC2_CR0_IDE_ENABLE)
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upc_found2(sc, "wdc", UPC_PORT_IDECMDBASE, 8,
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UPC_PORT_IDECTLBASE, 2, &sc->sc_wintr);
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/* Parallel */
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switch (cr[1] & UPC2_CR1_LPT_MASK) {
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case UPC2_CR1_LPT_3BC:
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upc_found(sc, "lpt", 0x3bc, LPT_NPORTS, &sc->sc_pintr);
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break;
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case UPC2_CR1_LPT_378:
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upc_found(sc, "lpt", 0x378, LPT_NPORTS, &sc->sc_pintr);
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break;
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case UPC2_CR1_LPT_278:
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upc_found(sc, "lpt", 0x278, LPT_NPORTS, &sc->sc_pintr);
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break;
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}
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/* UART1 */
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if (cr[2] & UPC2_CR2_UART1_ENABLE) {
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switch (cr[2] & UPC2_CR2_UART1_MASK) {
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case UPC2_CR2_UART1_3F8:
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upc_found(sc, "com", 0x3f8, COM_NPORTS, &sc->sc_irq4);
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break;
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case UPC2_CR2_UART1_2F8:
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upc_found(sc, "com", 0x2f8, COM_NPORTS, &sc->sc_irq3);
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break;
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case UPC2_CR2_UART1_COM3:
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upc_found(sc, "com", upc2_com3_addr(cr[1]), COM_NPORTS,
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&sc->sc_irq4);
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break;
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case UPC2_CR2_UART1_COM4:
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upc_found(sc, "com", upc2_com4_addr(cr[1]), COM_NPORTS,
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&sc->sc_irq3);
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break;
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}
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}
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/* UART2 */
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if (cr[2] & UPC2_CR2_UART2_ENABLE) {
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switch (cr[2] & UPC2_CR2_UART2_MASK) {
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case UPC2_CR2_UART2_3F8:
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upc_found(sc, "com", 0x3f8, COM_NPORTS, &sc->sc_irq4);
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break;
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case UPC2_CR2_UART2_2F8:
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upc_found(sc, "com", 0x2f8, COM_NPORTS, &sc->sc_irq3);
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break;
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case UPC2_CR2_UART2_COM3:
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upc_found(sc, "com", upc2_com3_addr(cr[1]), COM_NPORTS,
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&sc->sc_irq4);
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break;
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case UPC2_CR2_UART2_COM4:
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upc_found(sc, "com", upc2_com4_addr(cr[1]), COM_NPORTS,
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&sc->sc_irq3);
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break;
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}
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}
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}
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static void
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upc_found(struct upc_softc *sc, char const *devtype, int offset, int size,
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struct upc_irqhandle *uih)
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{
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struct upc_attach_args ua;
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int locs[UPCCF_NLOCS];
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ua.ua_devtype = devtype;
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ua.ua_offset = offset;
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ua.ua_iot = sc->sc_iot;
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bus_space_subregion(sc->sc_iot, sc->sc_ioh, offset, size, &ua.ua_ioh);
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ua.ua_irqhandle = uih;
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locs[UPCCF_OFFSET] = offset;
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config_found_sm_loc(&sc->sc_dev, "upc", locs, &ua,
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upc_print, config_stdsubmatch);
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}
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static void
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upc_found2(struct upc_softc *sc, char const *devtype, int offset, int size,
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int offset2, int size2, struct upc_irqhandle *uih)
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{
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struct upc_attach_args ua;
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int locs[UPCCF_NLOCS];
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ua.ua_devtype = devtype;
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ua.ua_offset = offset;
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ua.ua_iot = sc->sc_iot;
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bus_space_subregion(sc->sc_iot, sc->sc_ioh, offset, size, &ua.ua_ioh);
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bus_space_subregion(sc->sc_iot, sc->sc_ioh, offset2, size2,
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&ua.ua_ioh2);
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ua.ua_irqhandle = uih;
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locs[UPCCF_OFFSET] = offset;
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config_found_sm_loc(&sc->sc_dev, "upc", locs, &ua,
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upc_print, config_stdsubmatch);
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}
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void
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upc_intr_establish(struct upc_irqhandle *uih, int level, int (*func)(void *),
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void *arg) {
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uih->uih_level = level;
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uih->uih_func = func;
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uih->uih_arg = arg;
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/* Actual MD establishment will be handled later by bus attachment. */
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}
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static int
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upc2_com3_addr(int cr1)
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{
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switch (cr1 & UPC2_CR1_COM34_MASK) {
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case UPC2_CR1_COM34_338_238:
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return 0x338;
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case UPC2_CR1_COM34_3E8_2E8:
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return 0x3e8;
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case UPC2_CR1_COM34_2E8_2E0:
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return 0x2e8;
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case UPC2_CR1_COM34_220_228:
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return 0x220;
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}
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return -1;
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}
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static int
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upc2_com4_addr(int cr1)
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{
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switch (cr1 & UPC2_CR1_COM34_MASK) {
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case UPC2_CR1_COM34_338_238:
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return 0x238;
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case UPC2_CR1_COM34_3E8_2E8:
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return 0x2e8;
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case UPC2_CR1_COM34_2E8_2E0:
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return 0x2e0;
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case UPC2_CR1_COM34_220_228:
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return 0x228;
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}
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return -1;
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}
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static int
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upc_print(void *aux, char const *pnp)
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{
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struct upc_attach_args *ua = aux;
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if (pnp)
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aprint_normal("%s at %s", ua->ua_devtype, pnp);
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aprint_normal(" offset 0x%x", ua->ua_offset);
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return UNCONF;
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}
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int
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upc1_read_config(struct upc_softc *sc, int reg)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int retval;
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/* Switch into configuration mode. */
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG1, UPC1_CFGMAGIC_1);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_2);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_3);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG2,
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UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG1,
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(UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT) ^ 0xff);
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/* Read register. */
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bus_space_write_1(iot, ioh, UPC1_PORT_CRI, reg);
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retval = bus_space_read_1(iot, ioh, UPC1_PORT_CAP);
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/* Leave configuration mode. */
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bus_space_write_1(iot, ioh, UPC1_PORT_CRI, UPC1_CFGADDR_EXIT);
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bus_space_write_1(iot, ioh, UPC1_PORT_CAP, 0);
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return retval;
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}
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void
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upc1_write_config(struct upc_softc *sc, int reg, int val)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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/* Switch into configuration mode. */
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG1, UPC1_CFGMAGIC_1);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_2);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG2, UPC1_CFGMAGIC_3);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG2,
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UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT);
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bus_space_write_1(iot, ioh, UPC1_PORT_CFG1,
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(UPC1_PORT_CRI >> UPC1_CONFBASE_SHIFT) ^ 0xff);
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/* Read register. */
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bus_space_write_1(iot, ioh, UPC1_PORT_CRI, reg);
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bus_space_write_1(iot, ioh, UPC1_PORT_CAP, val);
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/* Leave configuration mode. */
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bus_space_write_1(iot, ioh, UPC1_PORT_CRI, UPC1_CFGADDR_EXIT);
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bus_space_write_1(iot, ioh, UPC1_PORT_CAP, 0);
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}
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int
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upc2_read_config(struct upc_softc *sc, int reg)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int retval;
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/* Switch into configuration mode. */
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
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/* Read register. */
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, reg);
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retval = bus_space_read_1(iot, ioh, UPC2_PORT_CFGDATA);
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/* Leave configuration mode. */
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_EXIT);
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return retval;
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}
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void
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upc2_write_config(struct upc_softc *sc, int reg, int val)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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/* Switch into configuration mode. */
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_ENTER);
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/* Write register. */
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, reg);
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGDATA, val);
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/* Leave configuration mode. */
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bus_space_write_1(iot, ioh, UPC2_PORT_CFGADDR, UPC2_CFGMAGIC_EXIT);
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}
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