ccb3b2f232
and the existing evbmips/gdium support. This has been tested on a lemote fuloong device (boots multiuser), should also support other lemote devices (maybe with minor adjustments, or adding missing drivers). There is some gdium support here too, but it may not be yet complete (someone with a gdium would need to have a look, hi macallan@ :) loongson kernels are 64bits only: the loongson2f has ressources located above the 2Gb physical address, and it's much easier to access it using XKPHYS than trying to make it fit in the limited 32bit kernel virtual space.
331 lines
11 KiB
C
331 lines
11 KiB
C
/* $OpenBSD: loongson2_machdep.c,v 1.11 2011/03/31 20:37:44 miod Exp $ */
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/*
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* Copyright (c) 2009, 2010 Miodrag Vallat.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/sysctl.h>
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#include <sys/kcore.h>
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#include <uvm/uvm_extern.h>
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#include <evbmips/loongson/autoconf.h>
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#include <evbmips/loongson/loongson_intr.h>
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#include <machine/kcore.h>
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#include <machine/cpu.h>
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#include <mips/pmon/pmon.h>
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#include <mips/bonito/bonitoreg.h>
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#include <mips/bonito/bonitovar.h>
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boolean_t is_memory_range(paddr_t, psize_t, psize_t);
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static void loongson2f_setup_window(uint, uint, uint64_t, uint64_t, uint64_t, uint);
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/*
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* Canonical crossbow assignments on Loongson 2F based designs.
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* Might need to move to a per-design header file in the future.
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*/
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#define MASTER_CPU 0
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#define MASTER_PCI 1
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#define WINDOW_CPU_LOW 0
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#define WINDOW_CPU_PCILO 1
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#define WINDOW_CPU_PCIHI 2
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#define WINDOW_CPU_DDR 3
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#define WINDOW_PCI_DDR 0
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#define DDR_PHYSICAL_BASE 0x0000000000000000UL /* memory starts at 0 */
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#define DDR_PHYSICAL_SIZE 0x0000000080000000UL /* up to 2GB */
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#define DDR_WINDOW_BASE 0x0000000080000000UL /* mapped at 2GB */
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#define PCI_RESOURCE_BASE 0x0000000000000000UL
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#define PCI_RESOURCE_SIZE 0x0000000080000000UL
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#define PCI_DDR_BASE 0x0000000080000000UL /* PCI->DDR at 2GB */
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/* bonito interrupt mappings */
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const struct bonito_irqmap loongson2e_irqmap[BONITO_NDIRECT] = {
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{ "mbox0", BONITO_INTR_MBOX + 0, IRQ_F_INT0 },
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{ "mbox1", BONITO_INTR_MBOX + 1, IRQ_F_INT0 },
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{ "mbox2", BONITO_INTR_MBOX + 2, IRQ_F_INT0 },
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{ "mbox3", BONITO_INTR_MBOX + 3, IRQ_F_INT0 },
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{ "dmardy", BONITO_INTR_MBOX + 4, IRQ_F_INT0 },
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{ "dmaempty", BONITO_INTR_MBOX + 5, IRQ_F_INT0 },
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{ "copyrdy", BONITO_INTR_MBOX + 6, IRQ_F_INT0 },
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{ "copyempty", BONITO_INTR_MBOX + 7, IRQ_F_INT0 },
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{ "coperr", BONITO_INTR_MBOX + 8, IRQ_F_INT1 },
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{ "pciirq", BONITO_INTR_MBOX + 9, IRQ_F_INT0 },
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{ "mastererr", BONITO_INTR_MBOX + 10, IRQ_F_INT1 },
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{ "systemerr", BONITO_INTR_MBOX + 11, IRQ_F_INT1 },
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{ "dramerr", BONITO_INTR_MBOX + 12, IRQ_F_INT1 },
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{ "retryerr", BONITO_INTR_MBOX + 13, IRQ_F_INT1 },
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{ NULL, BONITO_INTR_MBOX + 14, 0 },
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{ NULL, BONITO_INTR_MBOX + 15, 0 },
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{ "gpio0", BONITO_INTR_GPIO + 0, IRQ_F_INT0 },
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{ "gpio1", BONITO_INTR_GPIO + 1, IRQ_F_INT0 },
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{ "gpio2", BONITO_INTR_GPIO + 2, IRQ_F_INT0 },
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{ "gpio3", BONITO_INTR_GPIO + 3, IRQ_F_INT0 },
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{ "gpio4", BONITO_INTR_GPIO + 4, IRQ_F_INT0 },
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{ "gpio5", BONITO_INTR_GPIO + 5, IRQ_F_INT0 },
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{ "gpio6", BONITO_INTR_GPIO + 6, IRQ_F_INT0 },
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{ "gpio7", BONITO_INTR_GPIO + 7, IRQ_F_INT0 },
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{ "gpio8", BONITO_INTR_GPIO + 8, IRQ_F_INT0 },
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{ "gpin0", BONITO_INTR_GPIN + 0, IRQ_F_INT0 },
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{ "gpin1", BONITO_INTR_GPIN + 1, IRQ_F_INT0 },
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{ "gpin2", BONITO_INTR_GPIN + 2, IRQ_F_INT0 },
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{ "gpin3", BONITO_INTR_GPIN + 3, IRQ_F_INT0 },
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{ "gpin4", BONITO_INTR_GPIN + 4, IRQ_F_INT0 },
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{ "gpin5", BONITO_INTR_GPIN + 5, IRQ_F_INT0 },
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{ NULL, BONITO_INTR_GPIN + 6, 0 },
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};
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const struct bonito_irqmap loongson2f_irqmap[BONITO_NDIRECT] = {
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{ "gpio0", LOONGSON_INTR_GPIO0, IRQ_F_INT0 },
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{ "gpio1", LOONGSON_INTR_GPIO1, IRQ_F_INT0 },
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{ "gpio2", LOONGSON_INTR_GPIO2, IRQ_F_INT0 },
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{ "gpio3", LOONGSON_INTR_GPIO3, IRQ_F_INT0 },
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{ "pci inta", LOONGSON_INTR_PCIA, IRQ_F_INT0 },
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{ "pci intb", LOONGSON_INTR_PCIB, IRQ_F_INT0 },
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{ "pci intc", LOONGSON_INTR_PCIC, IRQ_F_INT0 },
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{ "pci intd", LOONGSON_INTR_PCID, IRQ_F_INT0 },
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{ "pci perr", LOONGSON_INTR_PCI_PARERR, IRQ_F_EDGE|IRQ_F_INT1 },
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{ "pci serr", LOONGSON_INTR_PCI_SYSERR, IRQ_F_EDGE|IRQ_F_INT1 },
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{ "denali", LOONGSON_INTR_DRAM_PARERR, IRQ_F_INT1 },
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{ "mips int0", LOONGSON_INTR_INT0, IRQ_F_INT0 },
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{ "mips int1", LOONGSON_INTR_INT1, IRQ_F_INT1 },
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{ "mips int2", LOONGSON_INTR_INT2, IRQ_F_INT2 },
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{ "mips int3", LOONGSON_INTR_INT3, IRQ_F_INT3 },
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};
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/*
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* Setup memory mappings for Loongson 2E processors.
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*/
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void
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loongson2e_setup(paddr_t memlo, paddr_t memhi,
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vaddr_t vkernstart, vaddr_t vkernend, bus_dma_tag_t t)
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{
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if (memhi > ((DDR_PHYSICAL_SIZE - BONITO_PCIHI_BASE) >> 20)) {
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pmon_printf("WARNING! %d MB of memory will not be used",
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memhi - ((DDR_PHYSICAL_SIZE - BONITO_PCIHI_BASE) >> 20));
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memhi = (DDR_PHYSICAL_SIZE - BONITO_PCIHI_BASE) >> 20;
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}
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physmem = btoc(memlo + memhi);
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/* do NOT stomp on exception area */
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/* mips_page_physload() will skip the kernel */
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mem_clusters[0].start = DDR_PHYSICAL_BASE;
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mem_clusters[0].size = memlo;
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mem_cluster_cnt = 1;
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if (memhi != 0) {
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mem_clusters[1].start = BONITO_PCIHI_BASE;
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mem_clusters[1].size = memhi;
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mem_cluster_cnt = 2;
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}
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t->_wbase = PCI_DDR_BASE;
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t->_bounce_alloc_lo = DDR_PHYSICAL_BASE;
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t->_bounce_alloc_hi = DDR_PHYSICAL_BASE + DDR_PHYSICAL_SIZE;
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}
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/*
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* Setup memory mappings for Loongson 2F processors.
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*/
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void
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loongson2f_setup(paddr_t memlo, paddr_t memhi,
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vaddr_t vkernstart, vaddr_t vkernend, bus_dma_tag_t t)
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{
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/*
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* Because we'll only set up a 2GB window for the PCI bus to
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* access local memory, we'll limit ourselves to 2GB of usable
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* memory as well.
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*
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* Note that this is a bad justification for this; it should be
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* possible to setup a 1GB PCI space / 3GB memory access window,
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* and use bounce buffers if physmem > 3GB; but at the moment
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* there is no need to solve this problem until Loongson 2F-based
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* hardware with more than 2GB of memory is commonly encountered.
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*
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* Also note that, despite the crossbar window registers being
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* 64-bit wide, the upper 32-bit always read back as zeroes, so
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* it is dubious whether it is possible to use more than a 4GB
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* address space... and thus more than 2GB of physical memory.
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*/
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physmem = btoc(memlo + memhi);
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if (physmem > btoc(DDR_PHYSICAL_SIZE)) {
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pmon_printf("WARNING! %d MB of memory will not be used",
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(physmem >> 20) - (DDR_PHYSICAL_SIZE >> 20));
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memhi = DDR_PHYSICAL_SIZE - btoc(256 << 20);
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}
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physmem = btoc(memlo + memhi);
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/*
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* PMON configures the system with only the low 256MB of memory
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* accessible.
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*
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* We need to reprogram the address windows in order to be able to
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* access the whole memory, both by the local processor and by the
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* PCI bus.
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*
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* To make our life easier, we'll setup the memory as a contiguous
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* range starting at 2GB, and take into account the fact that the
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* first 256MB are also aliased at address zero (which is where the
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* kernel is loaded, really).
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*/
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if (memhi != 0 ) {
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/* do NOT stomp on exception area */
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/* also make sure to skip the kernel */
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const paddr_t kernend = MIPS_KSEG0_TO_PHYS(round_page(vkernend));
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mem_clusters[0].start = DDR_WINDOW_BASE + kernend;
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mem_clusters[0].size = (memlo + memhi - kernend);
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t->_wbase = PCI_DDR_BASE;
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t->_bounce_alloc_lo = DDR_WINDOW_BASE;
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t->_bounce_alloc_hi = DDR_WINDOW_BASE + DDR_PHYSICAL_SIZE;
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mem_cluster_cnt = 1;
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} else {
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/* do NOT stomp on exception area */
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/* mips_page_physload() will skip the kernel */
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mem_clusters[0].start = DDR_PHYSICAL_BASE + PAGE_SIZE;
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mem_clusters[0].size = (memlo + memhi - PAGE_SIZE - PAGE_SIZE);
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t->_wbase = PCI_DDR_BASE;
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t->_bounce_alloc_lo = DDR_PHYSICAL_BASE;
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t->_bounce_alloc_hi = DDR_PHYSICAL_BASE + DDR_PHYSICAL_SIZE;
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mem_cluster_cnt = 1;
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}
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/*
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* Allow access to memory beyond 256MB, by programming the
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* Loongson 2F address window registers.
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* This also makes sure PCI->DDR accesses can use a contiguous
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* area regardless of the actual memory size.
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*/
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/*
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* Master #0 (cpu) window #0 allows access to the low 256MB
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* of memory at address zero onwards.
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* This window is inherited from PMON; we set it up just in case.
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*/
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loongson2f_setup_window(MASTER_CPU, WINDOW_CPU_LOW, DDR_PHYSICAL_BASE,
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~(0x0fffffffUL), DDR_PHYSICAL_BASE, MASTER_CPU);
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/*
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* Master #0 (cpu) window #1 allows access to the ``low'' PCI
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* space (from 0x10000000 to 0x1fffffff).
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* This window is inherited from PMON; we set it up just in case.
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*/
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loongson2f_setup_window(MASTER_CPU, WINDOW_CPU_PCILO, BONITO_PCILO_BASE,
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~(0x0fffffffUL), BONITO_PCILO_BASE, MASTER_PCI);
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/*
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* Master #1 (PCI) window #0 allows access to the memory space
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* by PCI devices at addresses 0x80000000 onwards.
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* This window is inherited from PMON, but its mask might be too
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* restrictive (256MB) so we make sure it matches our needs.
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*/
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loongson2f_setup_window(MASTER_PCI, WINDOW_PCI_DDR, PCI_DDR_BASE,
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~(DDR_PHYSICAL_SIZE - 1), DDR_PHYSICAL_BASE, MASTER_CPU);
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/*
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* Master #0 (CPU) window #2 allows access to a subset of the ``high''
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* PCI space (from 0x40000000 to 0x7fffffff only).
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*/
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loongson2f_setup_window(MASTER_CPU, WINDOW_CPU_PCIHI, LS2F_PCIHI_BASE,
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~((uint64_t)LS2F_PCIHI_SIZE - 1), LS2F_PCIHI_BASE, MASTER_PCI);
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/*
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* Master #0 (CPU) window #3 allows access to the whole memory space
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* at addresses 0x80000000 onwards.
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*/
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loongson2f_setup_window(MASTER_CPU, WINDOW_CPU_DDR, DDR_WINDOW_BASE,
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~(DDR_PHYSICAL_SIZE - 1), DDR_PHYSICAL_BASE, MASTER_CPU);
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}
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/*
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* Setup a window in the Loongson2F crossbar.
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*/
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static void
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loongson2f_setup_window(uint master, uint window, uint64_t base, uint64_t mask,
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uint64_t mmap, uint slave)
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{
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volatile uint64_t *awrreg;
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awrreg = (volatile uint64_t *)MIPS_PHYS_TO_XKPHYS(CCA_UNCACHED,
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LOONGSON_AWR_BASE(master, window));
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*awrreg = base;
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(void)*awrreg;
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awrreg = (volatile uint64_t *)MIPS_PHYS_TO_XKPHYS(CCA_UNCACHED,
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LOONGSON_AWR_SIZE(master, window));
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*awrreg = mask;
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(void)*awrreg;
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awrreg = (volatile uint64_t *)MIPS_PHYS_TO_XKPHYS(CCA_UNCACHED,
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LOONGSON_AWR_MMAP(master, window));
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*awrreg = mmap | slave;
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(void)*awrreg;
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}
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/*
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* Return whether a given physical address points to managed memory.
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* (used by /dev/mem)
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*/
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boolean_t
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is_memory_range(paddr_t pa, psize_t len, psize_t limit)
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{
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uint64_t fp, lp;
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int i;
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fp = atop(pa);
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lp = atop(round_page(pa + len));
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if (limit != 0 && lp > atop(limit))
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return FALSE;
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/*
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* Allow access to the low 256MB aliased region on 2F systems,
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* if we are accessing memory at 2GB onwards.
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*/
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if (pa < 0x10000000 && loongson_ver >= 0x2f) {
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fp += btoc(mem_clusters[0].start);
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lp += btoc(mem_clusters[0].start);
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}
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for (i = 0; i < VM_PHYSSEG_MAX; i++)
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if (fp >= btoc(mem_clusters[i].start) &&
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lp <= btoc(mem_clusters[i].start + mem_clusters[i].size))
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return TRUE;
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return FALSE;
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}
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