397 lines
10 KiB
C
397 lines
10 KiB
C
/* $NetBSD: footbridge_pci.c,v 1.2 1998/10/05 01:09:38 mark Exp $ */
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/*
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997,1998 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/irqhandler.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <arm32/footbridge/dc21285reg.h>
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#include <arm32/footbridge/dc21285mem.h>
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#include "isa.h"
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#if NISA > 0
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#include <dev/isa/isavar.h>
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#endif
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void footbridge_pci_attach_hook __P((struct device *,
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struct device *, struct pcibus_attach_args *));
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int footbridge_pci_bus_maxdevs __P((void *, int));
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pcitag_t footbridge_pci_make_tag __P((void *, int, int, int));
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void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *,
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int *, int *));
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pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int));
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void footbridge_pci_conf_write __P((void *, pcitag_t, int,
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pcireg_t));
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int footbridge_pci_intr_map __P((void *, pcitag_t, int, int,
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pci_intr_handle_t *));
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const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t));
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void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t,
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int, int (*)(void *), void *));
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void footbridge_pci_intr_disestablish __P((void *, void *));
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struct arm32_pci_chipset footbridge_pci_chipset = {
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NULL, /* conf_v */
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footbridge_pci_attach_hook,
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footbridge_pci_bus_maxdevs,
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footbridge_pci_make_tag,
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footbridge_pci_decompose_tag,
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footbridge_pci_conf_read,
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footbridge_pci_conf_write,
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NULL, /* intr_v */
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footbridge_pci_intr_map,
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footbridge_pci_intr_string,
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footbridge_pci_intr_establish,
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footbridge_pci_intr_disestablish
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};
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/*
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* PCI doesn't have any special needs; just use the generic versions
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* of these functions.
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*/
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struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = {
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0,
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0,
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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_bus_dmamap_sync,
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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/*
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* Currently we only support 12 devices as we select directly in the
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* type 0 config cycle
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* (See conf_{read,write} for more detail
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*/
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#define MAX_PCI_DEVICES 21
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/*static int
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pci_intr(void *arg)
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{
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printf("pci int %x\n", (int)arg);
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return(0);
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}*/
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void
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footbridge_pci_attach_hook(parent, self, pba)
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struct device *parent, *self;
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struct pcibus_attach_args *pba;
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{
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#ifdef PCI_DEBUG
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printf("footbridge_pci_attach_hook()\n");
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#endif
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/* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000);
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intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001);
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intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002);
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intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/
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}
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int
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footbridge_pci_bus_maxdevs(pcv, busno)
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void *pcv;
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int busno;
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{
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#ifdef PCI_DEBUG
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printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno);
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#endif
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return(MAX_PCI_DEVICES);
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}
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pcitag_t
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footbridge_pci_make_tag(pcv, bus, device, function)
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void *pcv;
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int bus, device, function;
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{
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#ifdef PCI_DEBUG
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printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n",
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pcv, bus, device, function);
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#endif
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return ((bus << 16) | (device << 11) | (function << 8));
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}
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void
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footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp)
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void *pcv;
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pcitag_t tag;
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int *busp, *devicep, *functionp;
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{
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#ifdef PCI_DEBUG
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printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n",
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pcv, tag, busp, devicep, functionp);
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#endif
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if (busp != NULL)
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*busp = (tag >> 16) & 0xff;
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if (devicep != NULL)
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*devicep = (tag >> 11) & 0x1f;
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if (functionp != NULL)
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*functionp = (tag >> 8) & 0x7;
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}
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pcireg_t
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footbridge_pci_conf_read(pcv, tag, reg)
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void *pcv;
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pcitag_t tag;
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int reg;
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{
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int bus, device, function;
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u_int address;
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pcireg_t data;
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footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function);
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if (bus == 0)
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/* Limited to 12 devices or we exceed type 0 config space */
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address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11);
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else
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address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) |
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(bus << 16);
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address |= (function << 8) | reg;
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data = *((unsigned int *)address);
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#ifdef PCI_DEBUG
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printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n",
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pcv, tag, reg, data);
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#endif
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return(data);
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}
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void
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footbridge_pci_conf_write(pcv, tag, reg, data)
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void *pcv;
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pcitag_t tag;
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int reg;
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pcireg_t data;
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{
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int bus, device, function;
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u_int address;
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footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function);
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if (bus == 0)
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address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11);
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else
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address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) |
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(bus << 16);
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address |= (function << 8) | reg;
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#ifdef PCI_DEBUG
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printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n",
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pcv, tag, reg, data);
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#endif
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*((unsigned int *)address) = data;
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}
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int
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footbridge_pci_intr_map(pcv, intrtag, pin, line, ihp)
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void *pcv;
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pcitag_t intrtag;
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int pin, line;
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pci_intr_handle_t *ihp;
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{
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int intr = -1;
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#ifdef PCI_DEBUG
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int bus, device, function;
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footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function);
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printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n",
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pcv, intrtag, pin, line, device);
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#endif
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/*
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* Only the line is used to map the interrupt.
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* The firmware is expected to setup up the interrupt
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* line as seen from the CPU
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* This means the firmware deals with the interrupt rotation
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* between slots etc.
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*
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* Perhaps the firmware should also to the final mapping
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* to a 21285 interrupt bit so the code below would be
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* completely MI.
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*/
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switch (line) {
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case PCI_INTERRUPT_PIN_NONE:
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case 0xff:
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/* No IRQ */
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printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
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*ihp = -1;
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return(1);
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break;
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#ifdef EBSA285
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/* This is machine dependant and needs to be moved */
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case PCI_INTERRUPT_PIN_A:
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intr = IRQ_PCI;
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break;
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case PCI_INTERRUPT_PIN_B:
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intr = IRQ_IN_L0;
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break;
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case PCI_INTERRUPT_PIN_C:
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intr = IRQ_IN_L1;
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break;
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case PCI_INTERRUPT_PIN_D:
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intr = IRQ_IN_L3;
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break;
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#endif
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default:
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/*
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* Experimental firmware feature ...
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*
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* If the interrupt line is in the range 0x80 to 0x8F
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* then the lower 4 bits indicate the ISA interrupt
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* bit that should be used.
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* If the interrupt line is in the range 0x40 to 0x5F
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* then the lower 5 bits indicate the actual DC21285
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* interrupt bit that should be used.
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*/
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if (line >= 0x40 && line <= 0x5f)
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intr = line & 0x1f;
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else if (line >= 0x80 && line <= 0x8f)
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intr = line;
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else {
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printf("footbridge_pci_intr_map: out of range interrupt pin %d\n", pin);
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*ihp = -1;
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return(1);
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}
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break;
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}
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#ifdef PCI_DEBUG
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printf("pin %d, line %d mapped to int %d\n", pin, line, intr);
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#endif
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*ihp = intr;
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return(0);
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}
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const char *
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footbridge_pci_intr_string(pcv, ih)
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void *pcv;
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pci_intr_handle_t ih;
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{
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static char irqstr[8]; /* 4 + 2 + NULL + sanity */
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#ifdef PCI_DEBUG
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printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih);
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#endif
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if (ih == 0)
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panic("footbridge_pci_intr_string: bogus handle 0x%lx\n", ih);
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#if NISA > 0
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if (ih >= 0x80 && ih <= 0x8f) {
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sprintf(irqstr, "isairq %ld", (ih & 0x0f));
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return(irqstr);
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}
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#endif
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sprintf(irqstr, "irq %ld", ih);
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return(irqstr);
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}
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void *
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footbridge_pci_intr_establish(pcv, ih, level, func, arg)
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void *pcv;
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pci_intr_handle_t ih;
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int level, (*func) __P((void *));
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void *arg;
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{
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void *intr;
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int length;
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char *string;
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#ifdef PCI_DEBUG
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printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n",
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pcv, ih, level, func, arg);
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#endif
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/* Copy the interrupt string to a private buffer */
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length = strlen(footbridge_pci_intr_string(pcv, ih));
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string = malloc(length + 1, M_DEVBUF, M_WAITOK);
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strcpy(string, footbridge_pci_intr_string(pcv, ih));
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#if NISA > 0
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/*
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* XXX the IDE driver will attach the interrupts in compat mode and
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* thus we need to fail this here.
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* This assumes that the interrupts are 14 and 15 which they are for
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* IDE compat mode.
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* Really the firmware should make this clear in the interrupt reg.
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*/
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if (ih >= 0x80 && ih <= 0x8d) {
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intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE,
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level, func, arg);
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} else
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#endif
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intr = intr_claim(ih, level, string, func, arg);
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return(intr);
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}
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void
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footbridge_pci_intr_disestablish(pcv, cookie)
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void *pcv;
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void *cookie;
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{
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#ifdef PCI_DEBUG
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printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n",
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pcv, cookie);
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#endif
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/* XXXX Need to free the string */
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intr_release(cookie);
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}
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