e225b7bd09
- Reorganize locking in UVM and provide extra serialisation for pmap(9). New lock order: [vmpage-owner-lock] -> pmap-lock. - Simplify locking in some pmap(9) modules by removing P->V locking. - Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs). - Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner. Add TLBSTATS option for x86 to collect statistics about TLB shootdowns. - Unify /dev/mem et al in MI code and provide required locking (removes kernel-lock on some ports). Also, avoid cache-aliasing issues. Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches formed the core changes of this branch.
307 lines
9.5 KiB
C
307 lines
9.5 KiB
C
/* $NetBSD: mem.c,v 1.28 2011/06/12 03:35:41 rmind Exp $ */
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/* $OpenBSD: mem.c,v 1.30 2007/09/22 16:21:32 krw Exp $ */
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/*
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* Copyright (c) 1998-2004 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1991,1992,1994, The University of Utah and
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* the Computer Systems Laboratory (CSL). All rights reserved.
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*
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* Subject to your agreements with CMU,
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* permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
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* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
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* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* CSL requests users of this software to return to csl-dist@cs.utah.edu any
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* improvements that they make and grant CSL redistribution rights.
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*
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* Utah $Hdr: mem.c 1.9 94/12/16$
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1992 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.28 2011/06/12 03:35:41 rmind Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/uio.h>
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#include <sys/types.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/file.h>
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#include <sys/bus.h>
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#include <sys/mutex.h>
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#include <uvm/uvm.h>
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#include <machine/iomod.h>
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#include <machine/autoconf.h>
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#include <machine/pmap.h>
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#include <hp700/hp700/machdep.h>
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#include <hp700/dev/cpudevs.h>
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#include <hp700/dev/viper.h>
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/* registers on the PCXL2 MIOC */
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struct l2_mioc {
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uint32_t pad[0x20]; /* 0x000 */
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uint32_t mioc_control; /* 0x080 MIOC control bits */
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uint32_t mioc_status; /* 0x084 MIOC status bits */
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uint32_t pad1[6]; /* 0x088 */
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uint32_t sltcv; /* 0x0a0 L2 cache control */
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#define SLTCV_AVWL 0x00002000 /* extra cycle for addr valid write low */
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#define SLTCV_UP4COUT 0x00001000 /* update cache on CPU castouts */
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#define SLTCV_EDCEN 0x08000000 /* enable error correction */
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#define SLTCV_EDTAG 0x10000000 /* enable diagtag */
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#define SLTCV_CHKTP 0x20000000 /* enable parity checking */
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#define SLTCV_LOWPWR 0x40000000 /* low power mode */
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#define SLTCV_ENABLE 0x80000000 /* enable L2 cache */
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#define SLTCV_BITS "\020\15avwl\16up4cout\24edcen\25edtag\26chktp\27lowpwr\30l2ena"
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uint32_t tagmask; /* 0x0a4 L2 cache tag mask */
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uint32_t diagtag; /* 0x0a8 L2 invalidates tag */
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uint32_t sltestat; /* 0x0ac L2 last logged tag read */
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uint32_t slteadd; /* 0x0b0 L2 pa of -- " -- */
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uint32_t pad2[3]; /* 0x0b4 */
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uint32_t mtcv; /* 0x0c0 MIOC timings */
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uint32_t ref; /* 0x0cc MIOC refresh timings */
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uint32_t pad3[4]; /* 0x0d0 */
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uint32_t mderradd; /* 0x0e0 addr of most evil mem error */
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uint32_t pad4; /* 0x0e4 */
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uint32_t dmaerr; /* 0x0e8 addr of most evil dma error */
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uint32_t dioerr; /* 0x0ec addr of most evil dio error */
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uint32_t gsc_timeout; /* 0x0f0 1-compl of GSC timeout delay */
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uint32_t hidmamem; /* 0x0f4 amount of phys mem installed */
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uint32_t pad5[2]; /* 0x0f8 */
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uint32_t memcomp[16]; /* 0x100 memory address comparators */
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uint32_t memmask[16]; /* 0x140 masks for -- " -- */
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uint32_t memtest; /* 0x180 test address decoding */
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uint32_t pad6[0xf]; /* 0x184 */
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uint32_t outchk; /* 0x1c0 address decoding output */
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uint32_t pad7[0x168]; /* 0x200 */
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uint32_t gsc15x_config; /* 0x7a0 writev enable */
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};
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struct mem_softc {
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device_t sc_dev;
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volatile struct vi_trs *sc_vp;
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volatile struct l2_mioc *sc_l2;
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};
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int memmatch(device_t, cfdata_t, void *);
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void memattach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(mem, sizeof(struct mem_softc), memmatch, memattach,
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NULL, NULL);
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int
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memmatch(device_t parent, cfdata_t cf, void *aux)
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{
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struct confargs *ca = aux;
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if (ca->ca_type.iodc_type != HPPA_TYPE_MEMORY ||
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ca->ca_type.iodc_sv_model != HPPA_MEMORY_PDEP)
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return 0;
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return 1;
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}
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void
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memattach(device_t parent, device_t self, void *aux)
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{
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struct pdc_iodc_minit pdc_minit;
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struct confargs *ca = aux;
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struct mem_softc *sc = device_private(self);
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int err, pagezero_cookie;
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char bits[128];
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sc->sc_dev = self;
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aprint_normal(":");
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pagezero_cookie = hp700_pagezero_map();
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/* XXX check if we are dealing w/ Viper */
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if (ca->ca_hpa == (hppa_hpa_t)VIPER_HPA) {
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sc->sc_vp = (struct vi_trs *)
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&((struct iomod *)ca->ca_hpa)->priv_trs;
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/* XXX other values seem to blow it up */
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if (sc->sc_vp->vi_status.hw_rev == 0) {
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uint32_t vic;
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int s, settimeout;
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switch (cpu_modelno) {
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case HPPA_BOARD_HP715_33:
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case HPPA_BOARD_HP715S_33:
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case HPPA_BOARD_HP715T_33:
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case HPPA_BOARD_HP715_50:
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case HPPA_BOARD_HP715S_50:
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case HPPA_BOARD_HP715T_50:
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case HPPA_BOARD_HP715_75:
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case HPPA_BOARD_HP725_50:
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case HPPA_BOARD_HP725_75:
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settimeout = 1;
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break;
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default:
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settimeout = 0;
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break;
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}
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if (device_cfdata(self)->cf_flags & 1)
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settimeout = !settimeout;
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snprintb(bits, sizeof(bits), VIPER_BITS, VI_CTRL);
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aprint_normal(" viper rev %x, ctrl %s",
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sc->sc_vp->vi_status.hw_rev, bits);
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s = splhigh();
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vic = VI_CTRL;
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((struct vi_ctrl *)&vic)->core_den = 0;
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((struct vi_ctrl *)&vic)->sgc0_den = 0;
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((struct vi_ctrl *)&vic)->sgc1_den = 0;
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((struct vi_ctrl *)&vic)->eisa_den = 1;
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((struct vi_ctrl *)&vic)->core_prf = 1;
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if (settimeout &&
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((struct vi_ctrl *)&vic)->vsc_tout == 0)
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/* clks */
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((struct vi_ctrl *)&vic)->vsc_tout = 850;
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sc->sc_vp->vi_control = vic;
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__asm __volatile("stwas %1, 0(%0)"
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:: "r" (&VI_CTRL), "r" (vic) : "memory");
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splx(s);
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#ifdef DEBUG
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snprintb(bits, sizeof(bits), VIPER_BITS, VI_CTRL);
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printf (" >> %s", bits);
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#endif
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} else
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sc->sc_vp = NULL;
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} else
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sc->sc_vp = NULL;
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err = pdcproc_iodc_ninit(&pdc_minit, ca->ca_hpa, PAGE0->imm_spa_size);
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if (err < 0)
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pdc_minit.max_spa = PAGE0->imm_max_mem;
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hp700_pagezero_unmap(pagezero_cookie);
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aprint_normal(" size %d", pdc_minit.max_spa / (1024*1024));
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if (pdc_minit.max_spa % (1024*1024))
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aprint_normal(".%d", pdc_minit.max_spa % (1024*1024));
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aprint_normal("MB");
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/* L2 cache controller is a part of the memory controller on PCXL2 */
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if (hppa_cpu_info->hci_cputype == hpcxl2) {
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sc->sc_l2 = (struct l2_mioc *)ca->ca_hpa;
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#ifdef DEBUG
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snprintb(bits, sizeof(bits), SLTCV_BITS, sc->sc_l2->sltcv);
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printf(", sltcv %s", bits);
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#endif
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/* sc->sc_l2->sltcv |= SLTCV_UP4COUT; */
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if (sc->sc_l2->sltcv & SLTCV_ENABLE) {
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uint32_t tagmask = sc->sc_l2->tagmask >> 20;
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aprint_normal(", %dMB L2 cache", tagmask + 1);
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}
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}
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aprint_normal("\n");
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}
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void
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viper_setintrwnd(uint32_t mask)
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{
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device_t dv;
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struct mem_softc *sc;
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dv = device_find_by_driver_unit("mem", 0);
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sc = device_private(dv);
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if (sc->sc_vp)
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sc->sc_vp->vi_intrwd;
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}
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void
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viper_eisa_en(void)
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{
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device_t dv;
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struct mem_softc *sc;
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dv = device_find_by_driver_unit("mem", 0);
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sc = device_private(dv);
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if (sc->sc_vp) {
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int pagezero_cookie;
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uint32_t vic;
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int s;
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pagezero_cookie = hp700_pagezero_map();
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s = splhigh();
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vic = VI_CTRL;
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((struct vi_ctrl *)&vic)->eisa_den = 0;
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sc->sc_vp->vi_control = vic;
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__asm __volatile("stwas %1, 0(%0)"
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:: "r" (&VI_CTRL), "r" (vic) : "memory");
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splx(s);
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hp700_pagezero_unmap(pagezero_cookie);
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}
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}
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