5f7e80a834
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the Giano system simulator. eMIPS is a platform developed at Microsoft Research for researching reconfigurable computing. eMIPS allows dynamic loading and scheduling of application-specific circuits for the purpose of accelerating computations based on the current workload. NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research by Alessandro Forin and Neil Pittman. Microsoft Corporation has donated full copyright to The NetBSD Foundation. Platform support for eMIPS is the first part of Microsoft's contribution. The second part includes the hardware accelerator framework and will be proposed on tech-kern soon.
930 lines
47 KiB
C
930 lines
47 KiB
C
/* $NetBSD: emipsreg.h,v 1.1 2011/01/26 01:18:51 pooka Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code was written by Alessandro Forin and Neil Pittman
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* at Microsoft Research and contributed to The NetBSD Foundation
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* by Microsoft Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Reference:
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* TBD MSR techreport by Richard Pittman and Alessandro Forin
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*
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* Definitions for the Xilinx ML40x dev boards with MSR's eMIPS.
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*/
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#ifndef _MIPS32_EMIPS_EMIPSREG_H_
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#define _MIPS32_EMIPS_EMIPSREG_H_ 1
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/*
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* Peripheral Mapping Table (PMT) definitions
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*
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* Each entry in this table holds the physical address of a section of peripherals
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* and the tag for the type of peripherals in that section.
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* Peripherals of the same type go into the same section, which is subdivided
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* as appropriate for that peripheral type.
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* Each section is at least 64KB wide, each subdivision is at least 4KB wide.
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*
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* NB: This table grows *down* from the top of the address space
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* The value 0xffffffff for an entry indicates the section is not populated.
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* The tag 0xffff is therefore invalid.
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* The end-of-table is indicated by the first invalid entry.
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*
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* Entries in the table are (preferably) in the processor's own byteorder.
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* The first entry is for the table itself and has a known tag.
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* From this software can verify the byteorder is correct.
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*
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* For each section we also define here its favorite placement in the address space.
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* Software should verify the table for the ultimate truth, peripherals might
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* or might not be present in the FPGA bitfile being used.
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*
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*/
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#ifndef __ASSEMBLER__
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struct _Pmt {
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volatile uint16_t TopOfPhysicalAddress;
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volatile uint16_t Tag;
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};
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#define ThePmt (((struct _Pmt *)0)-1)
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#endif /* !__ASSEMBLER__ */
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/*
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* Peripheral tags
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*/
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# define PMTTAG_END_OF_TABLE 0xffff /* required, last entry */
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# define PMTTAG_BRAM 0
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# define PMTTAG_PMT 1 /* required, first entry */
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# define PMTTAG_SRAM 2
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# define PMTTAG_DDRAM 3
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# define PMTTAG_FLASH 4
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# define PMTTAG_INTERRUPT_CONTROLLER 5
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# define PMTTAG_USART 6
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# define PMTTAG_TIMER 7
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# define PMTTAG_WATCHDOG 8
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# define PMTTAG_GPIO 9
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# define PMTTAG_SYSTEM_ACE 10
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# define PMTTAG_LCD 11
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# define PMTTAG_PS2 12
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# define PMTTAG_VGA 13
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# define PMTTAG_ETHERNET 14
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# define PMTTAG_AC97 15
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# define PMTTAG_POWER_MGR 16
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# define PMTTAG_EXTENSION_CONTROLLER 17
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# define PMTTAG_ICAP 18
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# define PMTTAG_LAST_TAG_DEFINED 18
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/*
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* Preferred addresses (nb: for the control registers of...)
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*/
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# define BRAM_DEFAULT_ADDRESS (0xffff << 16)
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# define SRAM_0_DEFAULT_ADDRESS (0xfffd << 16)
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# define DDRAM_0_DEFAULT_ADDRESS (0xfffc << 16)
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# define FLASH_0_DEFAULT_ADDRESS (0xfffb << 16)
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# define INTERRUPT_CONTROLLER_DEFAULT_ADDRESS (0xfffa << 16)
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# define USART_DEFAULT_ADDRESS (0xfff9 << 16)
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# define TIMER_DEFAULT_ADDRESS (0xfff8 << 16)
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# define WATCHDOG_DEFAULT_ADDRESS (0xfff7 << 16)
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# define GPIO_DEFAULT_ADDRESS (0xfff6 << 16)
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# define IDE_DEFAULT_ADDRESS (0xfff5 << 16)
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# define LCD_DEFAULT_ADDRESS (0xfff4 << 16)
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# define PS2_DEFAULT_ADDRESS (0xfff3 << 16)
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# define VGA_DEFAULT_ADDRESS (0xfff2 << 16)
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# define ETHERNET_DEFAULT_ADDRESS (0xfff1 << 16)
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# define POWER_MGR_DEFAULT_ADDRESS (0xfff0 << 16)
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# define AC97_DEFAULT_ADDRESS (0xffef << 16)
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# define EXTENSION_CONTROLLER_DEFAULT_ADDRESS (0xffee << 16)
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# define ICAP_DEFAULT_ADDRESS (0xffed << 16)
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/*
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* SRAM controller
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*/
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#ifndef __ASSEMBLER__
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struct _Sram {
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volatile uint32_t BaseAddressAndTag; /* rw */
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volatile uint32_t Control; /* rw */
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};
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#else
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# define SRAMBT 0
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# define SRAMST 4
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#endif /* !__ASSEMBLER__ */
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# define SRAMBT_TAG 0x0000ffff /* ro */
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# define SRAMBT_BASE 0xffff0000 /* rw */
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# define SRAMST_DELAY 0x0000000f /* rw */
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# define SRAMST_BURST_INTERLEAVED 0x00000010 /* ro */
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# define SRAMST_BURST_LINEAR 0x00000000 /* ro */
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# define SRAMST_BURST_ENABLE 0x00000020 /* rw */
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# define SRAMST_BURST_DISABLE 0x00000000 /* rw */
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# define SRAMST_CLOCK_MASK 0x00000040 /* rw */
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# define SRAMST_SLEEP 0x00000080 /* rw */
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# define SRAMST_PARITY 0x00000f00 /* rw */
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# define SRAMST_RESET 0x00001000 /* rw */
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# define SRAMST_BUS_8 0x00002000 /* rw */
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# define SRAMST_BUS_16 0x00004000 /* rw */
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# define SRAMST_BUS_32 0x00008000 /* rw */
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# define SRAMST_SIZE 0xffff0000 /* ro
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* in bytes, masked */
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/*
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* DDRAM controller
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*/
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#ifndef __ASSEMBLER__
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struct _Ddram {
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volatile uint32_t BaseAddressAndTag; /* rw */
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volatile uint32_t Control; /* rw */
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volatile uint32_t PreCharge; /* wo */
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volatile uint32_t Refresh; /* wo */
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};
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#else
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# define DDRAMBT 0
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# define DDRAMST 4
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# define DDRAMPC 8
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# define DDRAMRF 12
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# define DDRAMCTRL_SIZE 16
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#endif /* !__ASSEMBLER__ */
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# define DDRAMBT_TAG 0x0000ffff /* ro */
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# define DDRAMBT_BASE 0xffff0000 /* rw */
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# define DDRAMST_RST 0x00000001 /* rw */
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# define DDRAMST_CLR 0x00000002 /* rw */
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# define DDRAMST_TSTEN 0x00000004 /* rw */
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# define DDRAMST_BUF 0x00000008 /* rw */
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# define DDRAMST_CALDNE 0x00000010 /* ro */
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# define DDRAMST_CALFAIL 0x00000020 /* ro */
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# define DDRAMST_SERR 0x00000040 /* ro */
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# define DDRAMST_DERR 0x00000080 /* ro */
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# define DDRAMST_BURST 0x00000f00 /* ro */
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# define DDRAMST_OVF 0x00001000 /* ro */
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# define DDRAMST_BUS8 0x00002000 /* ro */
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# define DDRAMST_BUS16 0x00004000 /* ro */
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# define DDRAMST_BUS32 0x00008000 /* ro */
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# define DDRAMST_SIZE 0xffff0000 /* ro */
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/*
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* FLASH controller
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*/
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#ifndef __ASSEMBLER__
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struct _Flash {
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volatile uint32_t BaseAddressAndTag; /* rw */
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volatile uint32_t Control; /* rw */
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};
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#else
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# define FLASHBT 0
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# define FLASHST 4
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#endif /* !__ASSEMBLER__ */
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# define FLASHBT_TAG 0x0000ffff /* ro */
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# define FLASHBT_BASE 0xffff0000 /* rw */
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# define FLASHST_DELAY 0x0000000f /* rw */
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# define FLASHST_RESET_PIN 0x00000010 /* rw */
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# define FLASHST_RESET_CONTROLLER 0x00001000 /* rw */
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# define FLASHST_BUS_8 0x00002000 /* rw */
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# define FLASHST_BUS_16 0x00004000 /* rw */
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# define FLASHST_BUS_32 0x00008000 /* rw */
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# define FLASHST_SIZE 0xffff0000 /* ro
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* in bytes, masked */
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/*
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* ARM RPS Interrupt Controller (AIC)
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*/
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#ifndef __ASSEMBLER__
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struct _Aic {
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volatile uint32_t Tag; /* ro */
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volatile uint32_t IrqStatus; /* rw */
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volatile uint32_t IrqRawStatus; /* ro */
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volatile uint32_t IrqEnable; /* rw */
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volatile uint32_t IrqEnableClear;
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volatile uint32_t IrqSoft;
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};
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#else
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# define AICT 0
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# define AICS 4
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# define AICRS 8
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# define AICEN 12
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# define AICEC 16
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#endif /* !__ASSEMBLER__ */
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# define AIC_TIMER 0
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# define AIC_SOFTWARE 1
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# define AIC_GPIO 2
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# define AIC_WATCHDOG 3
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# define AIC_SYSTEM_ACE 4
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# define AIC_ETHERNET 5
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# define AIC_PS2 6
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# define AIC_AC97 7
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# define AIC_USART 9
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# define AIC_EXTENSION_CONTROLLER 10
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# define AIC_ICAP 11
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# define AIC_SYSTEM_ACE2 12
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# define AIC_VGA 13
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# define AIC_EXTENSION_2 29
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# define AIC_EXTENSION_1 30
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# define AIC_EXTENSION_0 31
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# define AIC_TIMER_BIT (1 << AIC_TIMER)
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# define AIC_SOFTWARE_BIT (1 << AIC_SOFTWARE)
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# define AIC_GPIO_BIT (1 << AIC_GPIO)
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# define AIC_WATCHDOG_BIT (1 << AIC_WATCHDOG)
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# define AIC_SYSTEM_ACE_BIT (1 << AIC_SYSTEM_ACE)
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# define AIC_ETHERNET_BIT (1 << AIC_ETHERNET)
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# define AIC_PS2_BIT (1 << AIC_PS2)
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# define AIC_AC97_BIT (1 << AIC_AC97)
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# define AIC_USART_BIT (1 << AIC_USART)
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# define AIC_EXTENSION_CONTROLLER_BIT (1 << AIC_EXTENSION_CONTROLLER)
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# define AIC_ICAP_BIT (1 << AIC_ICAP)
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# define AIC_SYSTEM_ACE2_BIT (1 << AIC_SYSTEM_ACE2)
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# define AIC_VGA_BIT (1 << AIC_VGA)
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# define AIC_EXTENSION_2_BIT (1 << AIC_EXTENSION_2)
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# define AIC_EXTENSION_1_BIT (1 << AIC_EXTENSION_1)
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# define AIC_EXTENSION_0_BIT (1 << AIC_EXTENSION_0)
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/*
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* General Purpose I/O pads controller (GPIO)
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*/
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#ifndef __ASSEMBLER__
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struct _Pio {
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volatile uint32_t Tag; /* ro value=9 NB: All other registers RESET to 0 */
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volatile uint32_t Enable; /* rw READ: 0 => high-z, 1 => In/Out based on DIRECTION
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* WRITE: 0 => no effect, 1 => pin is enabled for I/O */
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volatile uint32_t Disable; /* wo 0 => no effect, 1 => disabled, set in high-z */
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volatile uint32_t Direction; /* rw READ: 0 => input, 1 => output (if enabled)
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* WRITE: 0 => no-effect, 1 => output */
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volatile uint32_t OutDisable; /* wo 0 => no effect, 1 => set for input */
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volatile uint32_t PinData; /* rw READ: 0 => LOW, 1 => HIGH
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* WRITE: 0 => no effect, 1 => set pin HIGH */
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volatile uint32_t ClearData; /* wo 0 => no effect, 1 => set pin LOW */
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volatile uint32_t PinStatus; /* ro 0 => LOW, 1 => HIGH */
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volatile uint32_t IntrStatus; /* rw READ: 0 => none 1 => pending (regardless of INTRMASK)
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* WRITE: 0 => no-effect, 1 => clear if pending */
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volatile uint32_t IntrEnable; /* rw READ: 0 => none, 1 => enabled
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* WRITE: 0 => no-effect, 1 => enable */
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volatile uint32_t IntrDisable; /* wo 0 => no effect, 1 => disable */
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volatile uint32_t IntrTrigger; /* rw 0 => intr on level change, 1 => on transition */
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volatile uint32_t IntrNotLevel; /* rw 0 => HIGH, 1 => LOW -- Combinations:
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* Trig Lev InterruptOn..
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* 0 0 level high
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* 0 1 level low
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* 1 0 low to high transition
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* 1 1 high to low transition
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*/
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volatile uint32_t reserved[3]; /* ro padding to 64 bytes total */
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};
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#else
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# define PIOT 0
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# define PIOEN 4
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# define PIOD 8
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# define PIODIR 12
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# define PIOOD 16
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# define PIOPD 20
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# define PIOCD 24
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# define PIOPS 28
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# define PIOIS 32
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# define PIOIE 36
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# define PIOID 40
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# define PIOIT 44
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# define PIOINL 48
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#endif /* !__ASSEMBLER__ */
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/* DIP switches on SW1 and their known uses */
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# define PIO_SW1_1 0
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# define PIO_SW1_1_BIT (1 << PIO_SW1_1)
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# define PIO_SW1_2 1
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# define PIO_SW1_2_BIT (1 << PIO_SW1_2)
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# define PIO_SW1_3 2
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# define PIO_SW1_3_BIT (1 << PIO_SW1_3)
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# define PIO_SW1_4 3
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# define PIO_SW1_4_BIT (1 << PIO_SW1_4)
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# define PIO_SW1_5 4
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# define PIO_SW1_5_BIT (1 << PIO_SW1_5)
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# define PIO_SW1_6 5
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# define PIO_SW1_6_BIT (1 << PIO_SW1_6)
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# define PIO_SW1_7 6
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# define PIO_SW1_7_BIT (1 << PIO_SW1_7)
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# define PIO_SW1_8 7
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# define PIO_SW1_8_BIT (1 << PIO_SW1_8)
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# define SW1_BOOT_FROM_FLASH PIO_SW1_1_BIT /* else USART */
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# define SW1_BOOT_FS_IN_FLASH PIO_SW1_2_BIT /* else serplexd via USART */
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# define SW1_BOOT_FROM_SRAM PIO_SW1_3_BIT /* else USART */
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/* LEDs */
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# define PIO_LED_NORTH 8
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# define PIO_LED_NORTH_BIT (1 << PIO_LED_NORTH)
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# define PIO_LED_EAST 9
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# define PIO_LED_EAST_BIT (1 << PIO_LED_EAST)
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# define PIO_LED_SOUTH 10
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# define PIO_LED_SOUTH_BIT (1 << PIO_LED_SOUTH)
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# define PIO_LED_WEST 11
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# define PIO_LED_WEST_BIT (1 << PIO_LED_WEST)
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# define PIO_LED_CENTER 12
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# define PIO_LED_CENTER_BIT (1 << PIO_LED_CENTER)
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# define PIO_LED_GP0 13
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# define PIO_LED_GP0_BIT (1 << PIO_LED_GP0)
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# define PIO_LED_GP1 14
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# define PIO_LED_GP1_BIT (1 << PIO_LED_GP1)
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# define PIO_LED_GP2 15
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# define PIO_LED_GP2_BIT (1 << PIO_LED_GP2)
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# define PIO_LED_GP3 16
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# define PIO_LED_GP3_BIT (1 << PIO_LED_GP3)
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# define PIO_LED_ERROR1 17
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# define PIO_LED_ERROR1_BIT (1 << PIO_LED_ERROR1)
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# define PIO_LED_ERROR2 18
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# define PIO_LED_ERROR2_BIT (1 << PIO_LED_ERROR2)
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/* Buttons */
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# define PIO_BUTTON_NORTH 19
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# define PIO_BUTTON_NORTH_BIT (1 << PIO_BUTTON_NORTH)
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# define PIO_BUTTON_EAST 20
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# define PIO_BUTTON_EAST_BIT (1 << PIO_BUTTON_EAST)
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# define PIO_BUTTON_SOUTH 21
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# define PIO_BUTTON_SOUTH_BIT (1 << PIO_BUTTON_SOUTH)
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# define PIO_BUTTON_WEST 22
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# define PIO_BUTTON_WEST_BIT (1 << PIO_BUTTON_WEST)
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# define PIO_BUTTON_CENTER 23
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# define PIO_BUTTON_CENTER_BIT (1 << PIO_BUTTON_CENTER)
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/*
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* Universal Synch/Asynch Receiver/Transmitter (USART)
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*/
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#ifndef __ASSEMBLER__
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struct _Usart {
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volatile uint32_t Tag; /* ro */
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volatile uint32_t Control; /* rw */
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volatile uint32_t IntrEnable;
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volatile uint32_t IntrDisable;
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volatile uint32_t IntrMask;
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volatile uint32_t ChannelStatus; /* all these with.. */
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volatile uint32_t RxData;
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volatile uint32_t TxData;
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volatile uint32_t Baud;
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volatile uint32_t Timeout;
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volatile uint32_t reserved[6]; /* ro padding to 64 bytes total */
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};
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#else
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# define USARTT 0
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# define USARTC 4
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# define USARTIE 8
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# define USARTID 12
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# define USARTM 16
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# define USARTST 20
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# define USARTRX 24
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# define USARTTX 28
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# define USARTBD 32
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# define USARTTO 36
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#endif /* !__ASSEMBLER__ */
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# define USC_RESET 0x00000001
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# define USC_RSTRX 0x00000004
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# define USC_RSTTX 0x00000008
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# define USC_RXEN 0x00000010
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# define USC_RXDIS 0x00000020
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# define USC_TXEN 0x00000040
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# define USC_TXDIS 0x00000080
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# define USC_RSTSTA 0x00000100
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# define USC_STTBRK 0x00000200
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# define USC_STPBRK 0x00000400
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# define USC_STTO 0x00000800
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# define USC_CLK_SENDA 0x00010000
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# define USC_BPC_9 0x00020000
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# define USC_CLKO 0x00040000
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# define USC_EVEN 0x00000000
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# define USC_ODD 0x00080000
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# define USC_SPACE 0x00100000 /* forced 0 */
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# define USC_MARK 0x00180000 /* forced 1 */
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# define USC_NONE 0x00200000
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# define USC_MDROP 0x00300000
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# define USC_BPC_5 0x00000000
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# define USC_BPC_6 0x00400000
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|
# define USC_BPC_7 0x00800000
|
|
# define USC_BPC_8 0x00c00000
|
|
# define USC_CLKDIV 0x0f000000
|
|
# define USC_CLKDIV_1 0x00000000
|
|
# define USC_CLKDIV_2 0x01000000
|
|
# define USC_CLKDIV_4 0x02000000
|
|
# define USC_CLKDIV_8 0x03000000
|
|
# define USC_CLKDIV_16 0x04000000
|
|
# define USC_CLKDIV_32 0x05000000
|
|
# define USC_CLKDIV_64 0x06000000
|
|
# define USC_CLKDIV_128 0x07000000
|
|
# define USC_CLKDIV_EXT 0x08000000
|
|
# define USC_1STOP 0x00000000
|
|
# define USC_1_5STOP 0x10000000
|
|
# define USC_2STOP 0x20000000
|
|
# define USC_ECHO 0x40000000 /* rx->tx, tx disabled */
|
|
# define USC_LOOPBACK 0x80000000 /* tx->rx, rx/tx disabled */
|
|
# define USC_ECHO2 0xc0000000 /* rx->tx, rx disabled */
|
|
|
|
# define USI_RXRDY 0x00000001
|
|
# define USI_TXRDY 0x00000002
|
|
# define USI_RXBRK 0x00000004
|
|
# define USI_ENDRX 0x00000008
|
|
# define USI_ENDTX 0x00000010
|
|
# define USI_OVRE 0x00000020
|
|
# define USI_FRAME 0x00000040
|
|
# define USI_PARE 0x00000080
|
|
# define USI_TIMEOUT 0x00000100
|
|
# define USI_TXEMPTY 0x00000200
|
|
|
|
/*
|
|
* Timer/Counter (TC)
|
|
*/
|
|
#ifndef __ASSEMBLER__
|
|
struct _Tc {
|
|
volatile uint32_t Tag; /* ro */
|
|
volatile uint32_t Control; /* rw */
|
|
volatile uint64_t FreeRunning;
|
|
volatile uint32_t DownCounterHigh; /* rw */
|
|
volatile uint32_t DownCounter; /* rw */
|
|
volatile uint32_t reserved[2]; /* ro padding to 32 bytes total */
|
|
};
|
|
#else
|
|
# define TCT 0
|
|
# define TCC 4
|
|
# define TCFH 8
|
|
# define TCFL 12
|
|
# define TCCH 16
|
|
# define TCCL 20
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
# define TCCT_ENABLE 0x00000001
|
|
# define TCCT_INT_ENABLE 0x00000002
|
|
# define TCCT_CLKO 0x00000008
|
|
# define TCCT_RESET 0x00000010
|
|
# define TCCT_FINTEN 0x00000020
|
|
# define TCCT_CLOCK 0x000000c0
|
|
# define TCCT_INTERRUPT 0x00000100
|
|
# define TCCT_FINT 0x00000200
|
|
# define TCCT_OVERFLOW 0x00000400
|
|
# define TCCT_OVERRUN 0x00000800
|
|
|
|
/*
|
|
* LCD controller
|
|
*/
|
|
#ifndef __ASSEMBLER__
|
|
struct _Lcd {
|
|
volatile uint32_t TypeAndTag; /* ro */
|
|
volatile uint32_t Control; /* rw */
|
|
volatile uint32_t Data; /* wo */
|
|
volatile uint32_t Refresh; /* wo */
|
|
};
|
|
#else
|
|
# define LCDBT 0
|
|
# define LCDST 4
|
|
# define LCDPC 8
|
|
# define LCDRF 12
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
# define LCDBT_TAG 0x0000ffff /* ro */
|
|
# define LCDBT_TYPE 0xffff0000 /* ro */
|
|
|
|
# define LCDST_RST 0x00000001 /* rw */
|
|
/* other bits are type-specific */
|
|
|
|
/*
|
|
* Watchdog Timer (WD)
|
|
*/
|
|
#ifndef __ASSEMBLER__
|
|
struct _Wd {
|
|
volatile uint32_t Tag; /* ro */
|
|
volatile uint32_t OvflMode;
|
|
volatile uint32_t ClockMode;
|
|
volatile uint32_t Control;
|
|
volatile uint32_t Status;
|
|
volatile uint32_t reserved[3]; /* ro padding to 32 bytes total */
|
|
};
|
|
#else
|
|
# define WDT 0
|
|
# define WDO 4
|
|
# define WDM 8
|
|
# define WDC 12
|
|
# define WDS 16
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
/*
|
|
* Power Management Controller (PMC)
|
|
*/
|
|
#ifndef __ASSEMBLER__
|
|
struct _Pmc {
|
|
volatile uint32_t Tag; /* ro */
|
|
volatile uint32_t SystemPowerEnable; /* rw */
|
|
volatile uint32_t SystemPowerDisable; /* wo */
|
|
volatile uint32_t PeripheralPowerEnable; /* rw */
|
|
volatile uint32_t PeripheralPowerDisable; /* wo */
|
|
volatile uint32_t reserved[3]; /* ro padding to 32 bytes total */
|
|
};
|
|
#else
|
|
# define PMCT 0
|
|
# define PMCSE 4
|
|
# define PMCSD 8
|
|
# define PMCPE 12
|
|
# define PMCPD 16
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
# define PMCSC_CPU 0x00000001
|
|
|
|
/* more as we get more.. */
|
|
# define PMCPC_USART 0x00000001
|
|
|
|
|
|
/*
|
|
* System ACE Controller (SAC)
|
|
*/
|
|
|
|
#ifndef __ASSEMBLER__
|
|
struct _Sac {
|
|
volatile uint32_t Tag; /*0x00000000 */
|
|
volatile uint32_t Control; /*0x00000004 */
|
|
volatile uint32_t reserved0[30];
|
|
volatile uint32_t BUSMODEREG; /*0x00000080 */
|
|
volatile uint32_t STATUS; /*0x00000084 */
|
|
volatile uint32_t ERRORREG; /*0x00000088 */
|
|
volatile uint32_t CFGLBAREG; /*0x0000008c */
|
|
volatile uint32_t MPULBAREG; /*0x00000090 */
|
|
volatile uint16_t VERSIONREG; /*0x00000094 */
|
|
volatile uint16_t SECCNTCMDREG; /*0x00000096 */
|
|
volatile uint32_t CONTROLREG; /*0x00000098 */
|
|
volatile uint16_t reserved1[1];
|
|
volatile uint16_t FATSTATREG; /*0x0000009e */
|
|
volatile uint32_t reserved2[8];
|
|
volatile uint32_t DATABUFREG[16]; /*0x000000c0 */
|
|
};
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
/* volatile uint32_t Tag; 0x00000000 */
|
|
# define SAC_TAG 0x0000ffff
|
|
|
|
/* volatile uint32_t Control; 0x00000004 */
|
|
# define SAC_SIZE 0x0000ffff
|
|
# define SAC_RST 0x00010000
|
|
# define SAC_BUS8 0x00020000
|
|
# define SAC_BUS16 0x00040000
|
|
# define SAC_BUS32 0x00080000
|
|
# define SAC_IRQ 0x00100000
|
|
# define SAC_BRDY 0x00200000
|
|
# define SAC_INTMASK 0x00c00000
|
|
# define SAC_TDELAY 0x0f000000
|
|
# define SAC_BUFW8 0x10000000
|
|
# define SAC_BUFW16 0x20000000
|
|
# define SAC_BUFW32 0x40000000
|
|
# define SAC_DEBUG 0x80000000
|
|
|
|
/* volatile uint32_t BUSMODEREG; 0x00000080 */
|
|
# define SAC_MODE16 0x00000001
|
|
|
|
/* volatile uint32_t STATUS; 0x00000084 */
|
|
# define SAC_CFGLOCK 0x00000001
|
|
# define SAC_MPULOCK 0x00000002
|
|
# define SAC_CFGERROR 0x00000004
|
|
# define SAC_CFCERROR 0x00000008
|
|
# define SAC_CFDETECT 0x00000010
|
|
# define SAC_DATABUFRDY 0x00000020
|
|
# define SAC_DATABUFMODE 0x00000040
|
|
# define SAC_CFGDONE 0x00000080
|
|
# define SAC_RDYFORCFCMD 0x00000100
|
|
# define SAC_CFGMODEPIN 0x00000200
|
|
# define SAC_CFGADDRPINS 0x0000e000
|
|
# define SAC_CFBSY 0x00020000
|
|
# define SAC_CFRDY 0x00040000
|
|
# define SAC_CFDWF 0x00080000
|
|
# define SAC_CFDSC 0x00100000
|
|
# define SAC_CFDRQ 0x00200000
|
|
# define SAC_CFCORR 0x00400000
|
|
# define SAC_CFERR 0x00800000
|
|
|
|
/* volatile uint32_t ERRORREG; 0x00000088 */
|
|
# define SAC_CARDRESETERR 0x00000001
|
|
# define SAC_CARDRDYERR 0x00000002
|
|
# define SAC_CARDREADERR 0x00000004
|
|
# define SAC_CARDWRITEERR 0x00000008
|
|
# define SAC_SECTORRDYERR 0x00000010
|
|
# define SAC_CFGADDRERR 0x00000020
|
|
# define SAC_CFGFAILED 0x00000040
|
|
# define SAC_CFGREADERR 0x00000080
|
|
# define SAC_CFGINSTRERR 0x00000100
|
|
# define SAC_CFGINITERR 0x00000200
|
|
# define SAC_CFBBK 0x00000800
|
|
# define SAC_CFUNC 0x00001000
|
|
# define SAC_CFIDNF 0x00002000
|
|
# define SAC_CFABORT 0x00004000
|
|
# define SAC_CFAMNF 0x00008000
|
|
|
|
/* volatile uint16_t VERSIONREG; 0x00000094 */
|
|
# define SAC_VERREV 0x000000ff
|
|
# define SAC_VERMINOR 0x00000f00
|
|
# define SAC_VERMAJOR 0x0000f000
|
|
|
|
/* volatile uint16_t SECCNTCMDREG; 0x00000096 */
|
|
# define SAC_SECCCNT 0x000000ff
|
|
# define SAC_CMD 0x00000700
|
|
# define SAC_CMD_RESETMEMCARD 0x00000100
|
|
# define SAC_CMD_IDENTIFYMEMCARD 0x00000200
|
|
# define SAC_CMD_READMEMCARDDATA 0x00000300
|
|
# define SAC_CMD_WRITEMEMCARDDATA 0x00000400
|
|
# define SAC_CMD_ABORT 0x00000600
|
|
|
|
/* volatile uint32_t CONTROLREG; 0x00000098 */
|
|
# define SAC_FORCELOCKREQ 0x00000001
|
|
# define SAC_LOCKREQ 0x00000002
|
|
# define SAC_FORCECFGADDR 0x00000004
|
|
# define SAC_FORCECFGMODE 0x00000008
|
|
# define SAC_CFGMODE 0x00000010
|
|
# define SAC_CFGSTART 0x00000020
|
|
# define SAC_CFGSEL 0x00000040
|
|
# define SAC_CFGRESET 0x00000080
|
|
# define SAC_DATABUFRDYIRQ 0x00000100
|
|
# define SAC_ERRORIRQ 0x00000200
|
|
# define SAC_CFGDONEIRQ 0x00000400
|
|
# define SAC_RESETIRQ 0x00000800
|
|
# define SAC_CFGPROG 0x00001000
|
|
# define SAC_CFGADDRBIT 0x0000e000
|
|
# define SAC_CFGADDR_0 0x00000000
|
|
# define SAC_CFGADDR_1 0x00002000
|
|
# define SAC_CFGADDR_2 0x00004000
|
|
# define SAC_CFGADDR_3 0x00006000
|
|
# define SAC_CFGADDR_4 0x00008000
|
|
# define SAC_CFGADDR_5 0x0000a000
|
|
# define SAC_CFGADDR_6 0x0000c000
|
|
# define SAC_CFGADDR_7 0x0000e000
|
|
# define SAC_CFGRSVD 0x00070000
|
|
|
|
/* volatile uint16_t FATSTATREG; 0x0000009e */
|
|
# define SAC_MBRVALID 0x00000001
|
|
# define SAC_PBRVALID 0x00000002
|
|
# define SAC_MBRFAT12 0x00000004
|
|
# define SAC_PBRFAT12 0x00000008
|
|
# define SAC_MBRFAT16 0x00000010
|
|
# define SAC_PBRFAT16 0x00000020
|
|
# define SAC_CALCFAT12 0x00000040
|
|
# define SAC_CALCFAT16 0x00000080
|
|
|
|
/*
|
|
* Extension Controller (EC)
|
|
*/
|
|
|
|
#define EC_MAX_BATS 5
|
|
#ifndef __ASSEMBLER__
|
|
struct _Ec {
|
|
volatile uint32_t Tag; /*0x00000000 */
|
|
volatile uint32_t Control; /*0x00000004 */
|
|
volatile uint32_t SlotStatusAndTag; /*0x00000008 */
|
|
volatile uint32_t BatOrSize[EC_MAX_BATS]; /*0x0000000c */
|
|
};
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
/* volatile uint32_t Tag; 0x00000000 */
|
|
# define ECT_TAG 0x0000ffff
|
|
|
|
/* volatile uint32_t Control; 0x00000004 */
|
|
# define ECC_SIZE 0x0000ffff
|
|
# define ECC_RST 0x00010000
|
|
# define ECC_IRQ 0x00020000 /* write-one-to-clear */
|
|
# define ECC_IRQ_ENABLE 0x00040000
|
|
# define ECC_INT_LOAD 0x00100000
|
|
# define ECC_INT_UNLOAD 0x00200000
|
|
# define ECC_SLOTNO 0xff000000
|
|
# define ECC_SLOTNO_SHIFT 24
|
|
# define ECC_WANTS_INTERRUPT 0x00400000 /* extension needs interrupt */
|
|
# define ECC_PRIVILEDGED 0x00800000 /* extension needs priv interface */
|
|
|
|
/* volatile uint32_t SlotStatusAndTag; 0x00000008 */
|
|
# define ECS_TAG 0x0000ffff /* of the selected slot */
|
|
# define ECS_STATUS 0x00ff0000
|
|
# define ECS_ABSENT 0x00000000 /* not loaded */
|
|
# define ECS_CONFIG 0x00010000 /* needs configuration */
|
|
# define ECS_RUN 0x00020000 /* running ok */
|
|
# define ECS_PM0 0x00030000 /* power management state 0 */
|
|
# define ECS_PM1 0x00040000 /* power management state 1 */
|
|
# define ECS_PM2 0x00050000 /* power management state 2 */
|
|
|
|
/* volatile uint32_t BatOrSize[5]; 0x0000000c */
|
|
/* In the CONFIG state reads the size (flipped decode mask) for the corresponding bat */
|
|
# define ECB_SIZE_NONE 0x00000000
|
|
# define ECB_SIZE_4 0x00000003
|
|
# define ECB_SIZE_8 0x00000007 /* and so on, 2^N */
|
|
/* In non-CONFIG states reads the value of the corresponding Base Address Translation */
|
|
/* In all states, writes back to the corresponding BAT */
|
|
# define ECB_BAT_VALID 0x00000001
|
|
# define ECB_BAT 0xfffffff8
|
|
|
|
/*
|
|
* Common interface for packet-based device interfaces (CPBDI)
|
|
*/
|
|
|
|
#ifndef __ASSEMBLER__
|
|
#define CPBDI_STRUCT_DECLARATION { \
|
|
volatile uint32_t Tag; /* ro */ \
|
|
volatile uint32_t Control; /* rw */ \
|
|
/* FIFO interface. Write-> input FIFO; Read-> output FIFO */ \
|
|
volatile uint32_t SizeAndFlags; \
|
|
volatile uint32_t BufferAddressHi32; \
|
|
volatile uint32_t BufferAddressLo32; /* write/read of this word acts */ \
|
|
volatile uint32_t Pad[3]; /* round to 32bytes */ \
|
|
}
|
|
|
|
struct _Cpbdi CPBDI_STRUCT_DECLARATION;
|
|
#else
|
|
# define CPBDIT 0
|
|
# define CPBDIC 4
|
|
# define CPBDIS 8
|
|
# define CPBDIH 12
|
|
# define CPBDIL 16
|
|
# define CPBDI_SIZE 32
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
/* Common defines for Control register */
|
|
# define CPBDI_RESET 0x00000001 /* autoclear */
|
|
# define CPBDI_INTEN 0x00000002 /* interrupt enable */
|
|
# define CPBDI_DONE 0x00000004 /* interrupt pending aka done */
|
|
# define CPBDI_IF_FULL 0x00000010 /* input fifo full */
|
|
# define CPBDI_OF_EMPTY 0x00000020 /* output fifo empty */
|
|
# define CPBDI_URUN 0x00000040 /* recvr ran out of buffers */
|
|
# define CPBDI_ERROR 0x80000000 /* unrecoverable error */
|
|
|
|
/* Common defines for SizeAndFlags register */
|
|
# define CPBDI_F_MASK 0xf0000000
|
|
# define CPBDI_F_DONE 0x80000000
|
|
# define CPBDI_F_XMIT 0x00000000
|
|
# define CPBDI_F_RECV 0x10000000
|
|
# define CPBDI_F_CMD 0x20000000
|
|
|
|
/*
|
|
* Ethernet interface (ENIC)
|
|
*/
|
|
|
|
#ifndef __ASSEMBLER__
|
|
struct _Enic CPBDI_STRUCT_DECLARATION;
|
|
#else
|
|
# define ENICT CPBDIT
|
|
# define ENICC CPBDIC
|
|
# define ENICS CPBDIS
|
|
# define ENICH CPBDIH
|
|
# define ENICL CPBDIL
|
|
# define ENIC_SIZE CPBDI_SIZE
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
# define EC_RESET CPBDI_RESET
|
|
# define EC_INTEN CPBDI_INTEN
|
|
# define EC_DONE CPBDI_DONE
|
|
# define EC_RXDIS 0x00000008 /* recv disabled */
|
|
# define EC_IF_FULL CPBDI_IF_FULL
|
|
# define EC_OF_EMPTY CPBDI_OF_EMPTY
|
|
# define EC_URUN CPBDI_URUN
|
|
# define EC_ERROR CPBDI_ERROR
|
|
# define EC_WMASK 0x0000000b /* user-writeable bits */
|
|
|
|
# define ES_F_MASK CPBDI_F_MASK
|
|
# define ES_F_DONE CPBDI_F_DONE
|
|
# define ES_F_XMIT CPBDI_F_XMIT
|
|
# define ES_F_RECV CPBDI_F_RECV
|
|
# define ES_F_CMD CPBDI_F_CMD
|
|
# define ES_S_MASK 0xFFFF
|
|
|
|
/* Command codes in a command buffer (first byte)
|
|
*/
|
|
#define ENIC_CMD_NOP 0x00
|
|
#define ENIC_CMD_GET_INFO 0x01
|
|
#ifndef __ASSEMBLER__
|
|
typedef struct {
|
|
uint8_t InputFifoSize;
|
|
uint8_t OutputFifoSize;
|
|
uint8_t CompletionFifoSize;
|
|
uint8_t ErrorCount;
|
|
uint16_t FramesDropped;
|
|
uint16_t Reserved;
|
|
} ENIC_INFO, *PENIC_INFO;
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
#define ENIC_CMD_GET_ADDRESS 0x02
|
|
#ifndef __ASSEMBLER__
|
|
typedef struct {
|
|
uint8_t Mac[6];
|
|
} ENIC_MAC, *PENIC_MAC;
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
/*
|
|
* Internal Configuration Access Point (ICAP) interface
|
|
*/
|
|
|
|
#ifndef __ASSEMBLER__
|
|
struct _Icap CPBDI_STRUCT_DECLARATION;
|
|
#else
|
|
# define ICAPT CPBDIT
|
|
# define ICAPC CPBDIC
|
|
# define ICAPS CPBDIS
|
|
# define ICAPH CPBDIH
|
|
# define ICAPL CPBDIL
|
|
# define ICAP_SIZE CPBDI_SIZE
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
# define ICAPC_RESET CPBDI_RESET
|
|
# define ICAPC_INTEN CPBDI_INTEN
|
|
# define ICAPC_DONE CPBDI_DONE
|
|
# define ICAPC_IF_FULL CPBDI_IF_FULL
|
|
# define ICAPC_OF_EMPTY CPBDI_OF_EMPTY
|
|
# define ICAPC_ERROR CPBDI_ERROR
|
|
# define ICAPC_WMASK 0x00000007 /* user-writeable bits */
|
|
|
|
# define ICAPS_F_MASK CPBDI_F_MASK
|
|
# define ICAPS_F_DONE CPBDI_F_DONE
|
|
# define ICAPS_F_XMIT CPBDI_F_XMIT
|
|
# define ICAPS_F_RECV CPBDI_F_RECV
|
|
# define ICAPS_F_CMD CPBDI_F_CMD /* TBD */
|
|
# define ICAPS_S_MASK 0x0FFFFFFF
|
|
|
|
/*
|
|
* Extensible Video Graphic Array (EVGA) interface
|
|
*/
|
|
|
|
#ifndef __ASSEMBLER__
|
|
struct _Evga CPBDI_STRUCT_DECLARATION;
|
|
#else
|
|
# define EVGAT CPBDIT
|
|
# define EVGAC CPBDIC
|
|
# define EVGAS CPBDIS
|
|
# define EVGAH CPBDIH
|
|
# define EVGAL CPBDIL
|
|
# define EVGA_SIZE CPBDI_SIZE
|
|
#endif /* !__ASSEMBLER__ */
|
|
|
|
# define EVGAC_RESET CPBDI_RESET
|
|
# define EVGAC_INTEN CPBDI_INTEN
|
|
# define EVGAC_DONE CPBDI_DONE
|
|
# define EVGAC_IF_FULL CPBDI_IF_FULL
|
|
# define EVGAC_OF_EMPTY CPBDI_OF_EMPTY
|
|
# define EVGAC_ERROR CPBDI_ERROR
|
|
# define EVGAC_WMASK 0x00000007 /* user-writeable bits */
|
|
|
|
# define EVGAS_F_MASK CPBDI_F_MASK
|
|
# define EVGAS_F_DONE CPBDI_F_DONE
|
|
# define EVGAS_F_XMIT CPBDI_F_XMIT
|
|
# define EVGAS_F_RECV CPBDI_F_RECV
|
|
# define EVGAS_F_CMD CPBDI_F_CMD
|
|
# define EVGAS_S_MASK 0x0FFFFFFF
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/* Command codes in a command buffer (first byte) */
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#define EVGA_CMD_NOP 0x00
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#define EVGA_CMD_IDENTIFY 0x01
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#ifndef __ASSEMBLER__
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typedef struct {
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uint8_t CommandEcho;
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uint8_t InterfaceVersion;
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uint16_t Size; /* of this structure, all bytes counted */
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uint16_t PciVendorId; /* See PCI catalog */
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uint16_t PciProductId; /* See PCI catalog */
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uint32_t StandardCaps; /* TBD */
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uint8_t InputFifoSize;
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uint8_t OutputFifoSize;
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uint8_t CompletionFifoSize;
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uint8_t ErrorCount;
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/* More as needed */
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} EVGA_IDENTIFY, *PEVGA_IDENTIFY;
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#endif /* !__ASSEMBLER__ */
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#define EVGA_IDENTIFY_BIG_ENDIAN 0x00
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#define EVGA_IDENTIFY_LITTLE_ENDIAN 0x80
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#define EVGA_IDENTIFY_VERSION_1 0x01
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#define EVGA_CMD_2D_SET_BASE 0x02
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#define EVGA_CMD_2D_GET_BASE 0x03
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#ifndef __ASSEMBLER__
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typedef struct {
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uint8_t CommandEcho;
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uint8_t Pad[3];
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uint32_t AddressLow32;
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uint32_t AddressHigh32;
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} EVGA_2D_BASE, *PEVGA_2D_BASE;
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#endif /* !__ASSEMBLER__ */
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#endif /* _MIPS32_EMIPS_EMIPSREG_H_ */
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