198 lines
4.1 KiB
ArmAsm
198 lines
4.1 KiB
ArmAsm
/* $NetBSD: srt0.S,v 1.7 1996/10/18 01:36:16 thorpej Exp $ */
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/*
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* Copyright (c) 1994 Paul Kranenburg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Paul Kranenburg.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/param.h>
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#include <machine/psl.h>
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#define CCFSZ 96
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.file "str0.s"
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.data
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.global _cputyp, _nbpg, _pgofset, _pgshift
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_cputyp:
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.word 1
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_nbpg:
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.word 1
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_pgofset:
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.word 1
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_pgshift:
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.word 1
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.text
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.globl start
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start:
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/*
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* Set up a stack.
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*/
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set start, %o1
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save %o1, -CCFSZ, %sp
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/*
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* Relocate.
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*/
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1: call 2f
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nop
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2: add %o7, (start-1b), %l0
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set start, %l1
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set _end, %o0
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sub %o0, %l1, %l2 ! length
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3: ld [%l0], %o0
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add %l0, 4, %l0
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st %o0, [%l1]
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subcc %l2, 4, %l2
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bg 3b
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add %l1, 4, %l1
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set 4f, %g1
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jmp %g1
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nop
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4:
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#ifdef notyet
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/*
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* Enable traps
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*/
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wr %g0, 0, %wim ! make sure we can set psr
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nop; nop; nop
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wr %g0, PSR_S|PSR_PS|PSR_PIL, %psr ! set initial psr
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nop; nop; nop
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wr %g0, 2, %wim ! set initial %wim (w1 invalid)
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rd %psr, %l0
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wr %l0, PSR_ET, %psr
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nop; nop; nop
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#endif
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/*
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* Clear BSS
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*/
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set _edata, %o0 ! bzero(edata, end - edata)
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set _end, %o1
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call _bzero
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sub %o1, %o0, %o1
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/*
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* Enable interrupts, but only above level 11. This enables "L1-A",
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* but avoids spurious interrupt bites from most other devices.
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*/
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rd %psr, %o0
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andn %o0, PSR_PIL, %o0
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wr %o0, 0xb00, %psr ! (11 << 8)
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nop; nop; nop
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/*
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* Set CPU type that we are running on.
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*/
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sethi %hi(_cputyp), %o0
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set 0x4000, %g7
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cmp %i0, %g7
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beq 5f
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nop
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/*
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* Save address of PROM vector (passed in %i0).
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*/
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sethi %hi(_promvec), %o1
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st %i0, [%o1 + %lo(_promvec)]
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mov CPU_SUN4C, %g4
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mov SUN4CM_PGSHIFT, %g5
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b,a 6f
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5:
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mov CPU_SUN4, %g4
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mov SUN4_PGSHIFT, %g5
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6:
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st %g4, [%o0 + %lo(_cputyp)]
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sethi %hi(_pgshift), %o0 ! pgshift = log2(nbpg)
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st %g5, [%o0 + %lo(_pgshift)]
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mov 1, %o0 ! nbpg = 1 << pgshift
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sll %o0, %g5, %g5
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sethi %hi(_nbpg), %o0 ! nbpg = bytes in a page
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st %g5, [%o0 + %lo(_nbpg)]
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sub %g5, 1, %g5
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sethi %hi(_pgofset), %o0 ! page offset = bytes in a page - 1
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st %g5, [%o0 + %lo(_pgofset)]
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call _main
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mov %i0, %o0
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ret
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restore
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#ifdef TIGHT
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/*
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* XXX - Space saving .div & .rem routines (small & non-negative numbres only)
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*/
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.align 4
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.global .div, .udiv
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! int n = 0; while (a >= b) { a -= b; n++; }; return n;
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.div:
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.udiv:
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cmp %o0, %o1
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bl 2f
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mov 0, %o5
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1:
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sub %o0, %o1, %o0
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cmp %o0, %o1
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bge 1b
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add %o5, 1, %o5
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2:
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retl
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mov %o5, %o0
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.align 4
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.global .rem, .urem
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! while (a>=b) a -= b; return a;
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.rem:
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.urem:
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cmp %o0, %o1
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bl 2f
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nop
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sub %o0, %o1, %o0
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1:
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cmp %o0, %o1
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bge,a 1b
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sub %o0, %o1, %o0
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2:
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retl
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nop
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#endif /* TIGHT */
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