257 lines
6.5 KiB
ArmAsm
257 lines
6.5 KiB
ArmAsm
/* $NetBSD: odroid_start.S,v 1.2 2014/04/14 19:45:40 reinoud Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_exynos.h"
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#include "opt_sscom.h"
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#include "opt_cpuoptions.h"
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#include "opt_cputypes.h"
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#include "opt_multiprocessor.h"
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#include "opt_arm_debug.h"
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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#include <arch/arm/samsung/exynos_reg.h>
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#include <arch/arm/samsung/exynos4_reg.h>
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#include <arch/arm/samsung/exynos5_reg.h>
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#include <evbarm/odroid/platform.h>
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RCSID("$NetBSD: odroid_start.S,v 1.2 2014/04/14 19:45:40 reinoud Exp $")
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#if defined(VERBOSE_INIT_ARM)
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#define XPUTC(n) mov r0, n; bl xputc
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#define XPUTC2(n) mov r0, n; blx r11
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#ifdef __ARMEB__
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#define COM_BSWAP
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#endif
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#else
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#define XPUTC(n)
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#define XPUTC2(n)
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#endif
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#define INIT_MEMSIZE 128
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#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * 0x100000 - L1_TABLE_SIZE)
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#define MD_CPU_HATCH _C_LABEL(exynos_cpu_hatch)
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/*
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* Kernel start routine for ODROID boards running on uboot firmware
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* At this point, this code has been loaded into SDRAM
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* and the MMU is off
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*/
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.section .start,"ax",%progbits
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.global _C_LABEL(odroid_start)
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_C_LABEL(odroid_start):
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#ifdef __ARMEB__
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setend be /* force big endian */
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#endif
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/* Move into supervisor mode and disable IRQs/FIQs. */
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cpsid if, #PSR_SVC32_MODE
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/*
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* Save any arguments passed to us. But since .start is not at
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* 0x80000000 * but .text is, we can't directly use the address that
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* the linker gave us directly. Convert the virtual address to the
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* physical address by using KERNEL_BASE_VOFFSET.
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*/
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movw r4, #:lower16:uboot_args
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movt r4, #:upper16:uboot_args
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sub r4, r4, #KERNEL_BASE_VOFFSET
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stmia r4, {r0-r3} // Save the arguments
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/*
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* For easy and early SoC / PoP dependency, retrieve the IDs
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*/
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#if 1
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mov r6, #EXYNOS_CORE_PBASE
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#else
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movw r6, #:lower16:EXYNOS_CORE_PBASE
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movt r6, #:upper16:EXYNOS_CORE_PBASE
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#endif
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ldr r0, [r6, #EXYNOS_PROD_ID_OFFSET] // load soc_id
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movw r4, #:lower16:exynos_soc_id
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movt r4, #:upper16:exynos_soc_id
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sub r4, r4, #KERNEL_BASE_VOFFSET
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str r0, [r4] // save soc_id
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mov r5, r0 // save soc_id
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#ifdef EXYNOS4
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ldr r0, [r6, #EXYNOS_PACKAGE_ID_OFFSET] // load pop_id
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movw r4, #:lower16:exynos_pop_id
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movt r4, #:upper16:exynos_pop_id
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sub r4, r4, #KERNEL_BASE_VOFFSET
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str r0, [r4] // save pop_id
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#endif
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/* Pick uart address and initial MMU table for the SoC */
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mov r2, #0
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ubfx r1, r5, #24, #8
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cmp r1, #0xe5
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movteq r2, #:upper16:(EXYNOS_CORE_PBASE + EXYNOS5_UART2_OFFSET)
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cmp r1, #0xe4
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movteq r2, #:upper16:(EXYNOS_CORE_PBASE + EXYNOS4_UART1_OFFSET)
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mcr p15, 0, r2, c13, c0, 3 // TPIDRURO set (uart address)
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/*
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* Turn on the SMP bit
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*/
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bl cortex_init
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XPUTC(#67)
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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adr r1, .Lmmu_init_table
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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bl arm_boot_l1pt_init
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XPUTC(#68)
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/*
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* Turn on the MMU, Caches, etc.
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*/
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#ifdef VERBOSE_INIT_ARM
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adr r11, xputc
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#endif
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movw lr, #:lower16:1f
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movt lr, #:upper16:1f
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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b arm_cpuinit
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.pushsection .text, "ax", %progbits
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.align 0
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1:
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XPUTC2(#90)
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#if defined(MULTIPROCESSOR)
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#endif /* MULTIPROCESSOR */
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XPUTC2(#13)
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XPUTC2(#10)
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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*/
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b start
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.popsection // back to .start
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/* NOTREACHED */
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#if defined(VERBOSE_INIT_ARM)
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.align 0
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.global xputc
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.type xputc,%function
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#define TIMO 0x25000
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xputc:
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mov r2, #TIMO
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mrc p15, 0, r3, c13, c0, 3 // TPIDRURO get (uart address)
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1:
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ldr r1, [r3, #SSCOM_UTRSTAT]
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#ifdef __ARMEB__
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rev r1, r1
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#endif
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tst r1, #UTRSTAT_TXEMPTY
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bne 2f
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subs r2, r2, #1
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bne 1b
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2:
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#ifdef __ARMEB__
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rev r0, r0
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#endif
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str r0, [r3, #SSCOM_UTXH]
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mov r2, #TIMO
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3:
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ldr r1, [r3, #SSCOM_UTRSTAT]
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#ifdef __ARMEB__
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rev r1, r1
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#endif
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tst r1, #UTRSTAT_TXSHIFTER_EMPTY
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bne 4f
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subs r2, r2, #1
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bne 3b
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4:
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bx lr
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#endif
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#include <arm/cortex/a9_mpsubr.S>
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#if EXYNOS_CORE_SIZE < EXYNOS4_CORE_SIZE
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#error EXYNOS_CORE_SIZE smaller than EXYNOS4_CORE_SIZE
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#endif
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#if EXYNOS_CORE_SIZE < EXYNOS5_CORE_SIZE
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#error EXYNOS_CORE_SIZE smaller than EXYNOS5_CORE_SIZE
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#endif
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.align 0
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.Lmmu_init_table:
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/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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#if KERNEL_BASE_VOFFSET
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/* Map physical addresses of kernel 1:1 PA:VA write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
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KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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#endif
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/* Map EXYNOS CORE (so console will work) */
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MMU_INIT(EXYNOS_CORE_VBASE, EXYNOS_CORE_PBASE,
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EXYNOS_CORE_SIZE / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* Map EXYNOS CORE (so console will work) */
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MMU_INIT(EXYNOS_CORE_PBASE, EXYNOS_CORE_PBASE,
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EXYNOS_CORE_SIZE / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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END(odroid_start)
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