337 lines
7.7 KiB
ArmAsm
337 lines
7.7 KiB
ArmAsm
/* $NetBSD: armadillo9_start.S,v 1.3 2006/02/13 12:24:21 hamajima Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include <arm/arm32/pte.h>
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#include "epcom.h"
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.section .start,"ax",%progbits
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.global _C_LABEL(armadillo9_start)
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_C_LABEL(armadillo9_start):
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/* make sure svc mode and all fiqs&irqs disabled */
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mov r0, #(PSR_SVC32_MODE | I32_bit | F32_bit)
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msr cpsr_c, r0
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/*
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* We will go ahead and disable the MMU here so that we don't
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* have to worry about flushing caches, etc.
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*
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* Note that we may not currently be running VA==PA, which means
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* we'll need to leap to the next insn after disabing the MMU.
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*/
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adr r8, Lunmapped
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bic r8, r8, #0xff000000 /* clear upper 8 bits */
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orr r8, r8, #0xc0000000 /* OR in physical base address */
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/*
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* Setup coprocessor 15.
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*/
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mrc p15, 0, r2, c1, c0, 0
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bic r2, r2, #CPU_CONTROL_MMU_ENABLE
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bic r2, r2, #CPU_CONTROL_DC_ENABLE
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bic r2, r2, #CPU_CONTROL_IC_ENABLE
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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mov pc, r8 /* Heave-ho! */
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Lunmapped:
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/* set temporary stack pointer */
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ldr sp, Ltable
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#ifdef VERBOSE_INIT_ARM
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/* initialize UART */
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bl init_UART
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#endif
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/* copy bootparam */
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bl copy_bootparam
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/* copy myself to virtual address */
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bl copy_myself
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/*
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* We want to construct a memory map that maps us
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* VA==PA (SDRAM at 0xc0000000). We create these
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* mappings uncached and unbuffered to be safe.
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*/
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/*
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* Step 1: Map the entire address space VA==PA.
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*/
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adr r4, Ltable
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ldr r0, [r4] /* r0 = &l1table */
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mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */
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mov r2, #(L1_S_SIZE) /* 1MB / section */
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mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */
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orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */
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1:
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str r3, [r0], #0x04
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add r3, r3, r2
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subs r1, r1, #1
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bgt 1b
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/*
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* Step 2: Map VA 0xf0000000->0xf00fffff to PA 0x80000000->0x800fffff.
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*/
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ldr r0, [r4]
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add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */
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mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */
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orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */
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orr r3, r3, #0x80000000
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str r3, [r0], #4
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/*
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* Step 3: Map VA 0xf0100000->0xf02fffff to PA 0x80800000->0x809fffff.
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*/
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mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */
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orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */
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orr r3, r3, #0x80000000
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orr r3, r3, #0x00800000
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str r3, [r0], #0x4
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add r3, r3, r2
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str r3, [r0], #0x4
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/* OK! Page table is set up. Give it to the CPU. */
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adr r0, Ltable
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ldr r0, [r0]
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mcr p15, 0, r0, c2, c0, 0
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/* Flush the old TLBs, just in case. */
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mcr p15, 0, r0, c8, c7, 0
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/* Set the Domain Access register. Very important! */
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mov r0, #1
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mcr p15, 0, r0, c3, c0, 0
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/* Get ready to jump to the "real" kernel entry point... */
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ldr r1, Lstart
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mov r1, r1 /* Make sure the load completes! */
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/* OK, let's enable the MMU. */
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mrc p15, 0, r2, c1, c0, 0
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orr r2, r2, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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/* CPWAIT sequence to make sure the MMU is on... */
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mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
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mov r2, r2 /* force it to complete */
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mov pc, r1 /* leap to kernel entry point! */
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#define BOOTPARAM_ADDRESS 0xc0000100
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#define BOOTPARAM_SIZE 0x0f00
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Ltable:
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.word armadillo9_start - L1_TABLE_SIZE
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Lstart:
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.word start
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Lsection:
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.word .start
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.word 0xc0200000
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.word __bss_start
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Lbootparam_address:
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.word BOOTPARAM_ADDRESS
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copy_myself:
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stmfd sp!, {r0-r5, lr}
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adr r0, Lsection
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ldmia r0, {r1, r2, r4} /* r1: kernel(load) start address */
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/* r2: kernel(virtual) start address */
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/* r3: kernel size */
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sub r3, r4, r2 /* r4: kernel(virtual) end address */
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add r5, r1, r3 /* r5: kernel(load) end address */
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#ifdef VERBOSE_INIT_ARM
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adr r0, Lmsg1 /* "copy kernel from " */
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bl print_str
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bl print_r1
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adr r0, Lmsg2 /* " to " */
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bl print_str
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bl print_r2
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adr r0, Lmsg3 /* " size " */
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bl print_str
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bl print_r3
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bl print_cr
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#endif
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1:
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ldr r0, [r5], #-4
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str r0, [r4], #-4
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cmp r5, r1
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bge 1b
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ldmfd sp!, {r0-r5, pc}
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copy_bootparam:
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stmfd sp!, {r0-r3, lr}
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mov r1, #BOOTPARAM_SIZE
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ldr r2, Lbootparam_address
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adr r3, _C_LABEL(bootparam)
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#ifdef VERBOSE_INIT_ARM
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adr r0, Lmsg0 /* "copy bootparam from " */
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bl print_str
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bl print_r2
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adr r0, Lmsg2 /* " to " */
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bl print_str
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bl print_r3
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adr r0, Lmsg3 /* " size " */
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bl print_str
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bl print_r1
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bl print_cr
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#endif
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1:
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ldr r0, [r2], #4
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str r0, [r3], #4
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subs r1, r1, #4
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bne 1b
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ldmfd sp!, {r0-r3, pc}
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#ifdef VERBOSE_INIT_ARM
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Lmsg0:
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.asciz "copy bootparam from "
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.align 0
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Lmsg1:
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.asciz "copy kernel from "
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.align 0
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Lmsg2:
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.asciz " to "
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.align 0
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Lmsg3:
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.asciz " size "
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.align 0
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#if NEPCOM > 0
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#define EP93XX_APB_UART1 0x808c0000
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#define EP93XX_APB_UART2 0x808d0000
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#ifndef CONUNIT
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#define CONUNIT 0
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#endif
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Lcomaddr:
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.word EP93XX_APB_UART1
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.word EP93XX_APB_UART2
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#endif
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init_UART:
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stmfd sp!, {r4-r5, lr}
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#if NEPCOM > 0
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ldr r4, Lcomaddr+(CONUNIT*4)
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ldr r5, [r4, #0x08]
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orr r5, r5, #0x10
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str r5, [r4, #0x08] /* enable FIFO */
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mov r5, #0x01
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str r5, [r4, #0x14] /* disable interrupt */
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#endif
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ldmfd sp!, {r4-r5, pc}
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print_char: /* char = r0 */
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stmfd sp!, {r4-r5, lr}
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#if NEPCOM > 0
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ldr r4, Lcomaddr+(CONUNIT*4)
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1:
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ldr r5, [r4, #0x18]
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tst r5, #0x20 /* check TXFF */
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bne 1b
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str r0, [r4, #0x00]
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#endif
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ldmfd sp!, {r4-r5, pc}
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print_cr:
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stmfd sp!, {r0, lr}
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#if NEPCOM > 0
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mov r0, #0x0d /* cr */
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bl print_char
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mov r0, #0x0a /* lf */
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bl print_char
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#endif
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ldmfd sp!, {r0, pc}
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print_str:
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stmfd sp!, {r0, r4, lr}
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#if NEPCOM > 0
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mov r4, r0
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1:
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ldrb r0, [r4], #1
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cmp r0, #0
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beq 2f
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bl print_char
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b 1b
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2:
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#endif
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ldmfd sp!, {r0, r4, pc}
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print_r3:
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stmfd sp!, {r0, r3-r6, lr}
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#if NEPCOM > 0
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mov r4, #28
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mov r5, #0xf
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1:
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and r6, r5, r3, ROR r4
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cmp r6, #10
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addlt r0, r6, #'0'
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addge r0, r6, #('a' - 0x0a)
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bl print_char
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subs r4, r4, #4
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bge 1b
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#endif
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ldmfd sp!, {r0, r3-r6, pc}
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#define print_register(reg) \
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stmfd sp!, {r3, lr} ;\
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mov r3, reg ;\
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bl print_r3 ;\
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ldmfd sp!, {r3, pc}
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print_r0:
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print_register(r0)
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print_r1:
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print_register(r1)
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print_r2:
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print_register(r2)
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#endif
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.global _C_LABEL(bootparam)
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_C_LABEL(bootparam):
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.space BOOTPARAM_SIZE
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