82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
/* $NetBSD: flscvar.h,v 1.5 1999/09/25 21:47:11 is Exp $ */
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/*
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* Copyright (c) 1997 Michael L. Hitch.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project
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* by Michael L. Hitch.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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struct flsc_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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struct isr sc_isr; /* Interrupt chain struct */
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volatile u_char *sc_reg; /* the registers */
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volatile u_char *sc_dmabase;
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int sc_active; /* Pseudo-DMA state vars */
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int sc_piomode;
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int sc_datain;
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int sc_tc;
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size_t sc_dmasize;
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size_t sc_dmatrans;
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char **sc_dmaaddr;
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size_t *sc_pdmalen;
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paddr_t sc_pa;
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char *sc_alignbuf;
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u_char sc_pad1[2]; /* XXX */
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u_char sc_unalignbuf[256];
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u_char sc_pad2[16];
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u_char sc_hardbits;
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u_char sc_portbits;
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u_char sc_csr;
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u_char sc_xfr_align;
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};
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#define FLSC_HB_DISABLED 0x01
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#define FLSC_HB_BUSID6 0x02
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#define FLSC_HB_SEAGATE 0x04
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#define FLSC_HB_SLOW 0x08
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#define FLSC_HB_SYNCHRON 0x10
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#define FLSC_HB_CREQ 0x20
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#define FLSC_HB_IACT 0x40
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#define FLSC_HB_MINT 0x80
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#define FLSC_PB_ESI 0x01
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#define FLSC_PB_EDI 0x02
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#define FLSC_PB_ENABLE_DMA 0x04
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#define FLSC_PB_DISABLE_DMA 0x00 /* Symmetric reasons */
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#define FLSC_PB_DMA_WRITE 0x08
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#define FLSC_PB_DMA_READ 0x00 /* Symmetric reasons */
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#define FLSC_PB_LED 0x10
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#define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI)
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#define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE)
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