ae4b76c8d3
in interrupt controllers in struct pic, and try to keep as much common code as possible. At the lowest (asm) level, this is done with CPP macros. The main structure is now struct intrsource, describing an established interrupt line, of any kind (soft/hard local apic/legacy apic/IO apic). For quick masking, there may be a maximum of 32 sources per CPU. Sources can be assigned to any CPU in the MP case, though currently they all go to the boot CPU.
154 lines
4.7 KiB
C
154 lines
4.7 KiB
C
/* $NetBSD: i8259.h,v 1.1 2002/11/22 15:23:47 fvdl Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)icu.h 5.6 (Berkeley) 5/9/91
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*/
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#ifndef _I386_I8259_H_
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#define _I386_I8259_H_
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#include <dev/isa/isareg.h>
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#ifndef _LOCORE
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/*
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* Interrupt "level" mechanism variables, masks, and macros
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*/
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extern unsigned i8259_imen; /* interrupt mask enable */
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extern unsigned i8259_setmask(unsigned);
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#define SET_ICUS() (outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
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extern void i8259_default_setup(void);
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extern void i8259_reinit(void);
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#endif /* !_LOCORE */
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/*
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* Interrupt enable bits -- in order of priority
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*/
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#define IRQ_SLAVE 2
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/*
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* Interrupt Control offset into Interrupt descriptor table (IDT)
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*/
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#define ICU_OFFSET 32 /* 0-31 are processor exceptions */
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#define ICU_LEN 16 /* 32-47 are ISA interrupts */
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#define ICU_HARDWARE_MASK
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/*
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* These macros are fairly self explanatory. If ICU_SPECIAL_MASK_MODE is
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* defined, we try to take advantage of the ICU's `special mask mode' by only
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* EOIing the interrupts on return. This avoids the requirement of masking and
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* unmasking. We can't do this without special mask mode, because the ICU
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* would also hold interrupts that it thinks are of lower priority.
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*
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* Many machines do not support special mask mode, so by default we don't try
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* to use it.
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*/
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#define IRQ_BIT(num) (1 << ((num) % 8))
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#define IRQ_BYTE(num) ((num) >> 3)
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#define i8259_late_ack(num)
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#ifdef ICU_SPECIAL_MASK_MODE
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#define i8259_asm_ack1(num)
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#define i8259_asm_ack2(num) \
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movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
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outb %al,$IO_ICU1
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#define i8259_asm_mask(num)
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#define i8259_asm_unmask(num) \
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movb $(0x60|(num%8)),%al /* specific EOI */ ;\
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outb %al,$ICUADDR
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#else /* ICU_SPECIAL_MASK_MODE */
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#ifndef AUTO_EOI_1
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#define i8259_asm_ack1(num) \
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movb $(0x60|(num%8)),%al /* specific EOI */ ;\
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outb %al,$IO_ICU1
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#else
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#define i8259_asm_ack1(num)
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#endif
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#ifndef AUTO_EOI_2
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#define i8259_asm_ack2(num) \
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movb $(0x60|(num%8)),%al /* specific EOI */ ;\
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outb %al,$IO_ICU2 /* do the second ICU first */ ;\
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movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
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outb %al,$IO_ICU1
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#else
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#define i8259_asm_ack2(num)
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#endif
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#ifdef PIC_MASKDELAY
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#define MASKDELAY pushl %eax ; inb $0x84,%al ; popl %eax
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#else
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#define MASKDELAY
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#endif
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#ifdef ICU_HARDWARE_MASK
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#define i8259_asm_mask(num) \
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movb _C_LABEL(i8259_imen) + IRQ_BYTE(num),%al ;\
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orb $IRQ_BIT(num),%al ;\
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movb %al,_C_LABEL(i8259_imen) + IRQ_BYTE(num) ;\
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MASKDELAY ;\
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outb %al,$(ICUADDR+1)
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#define i8259_asm_unmask(num) \
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cli ;\
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movb _C_LABEL(i8259_imen) + IRQ_BYTE(num),%al ;\
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andb $~IRQ_BIT(num),%al ;\
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movb %al,_C_LABEL(i8259_imen) + IRQ_BYTE(num) ;\
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MASKDELAY ;\
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outb %al,$(ICUADDR+1) ;\
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sti
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#else /* ICU_HARDWARE_MASK */
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#define i8259_asm_mask(num)
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#define i8259_asm_unmask(num)
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#endif /* ICU_HARDWARE_MASK */
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#endif /* ICU_SPECIAL_MASK_MODE */
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#endif /* !_I386_I8259_H_ */
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