319 lines
12 KiB
C
319 lines
12 KiB
C
/* $NetBSD: fpu_emulate.h,v 1.8 2001/02/18 20:05:58 chs Exp $ */
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/*
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* Copyright (c) 1995 Gordon Ross
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* Copyright (c) 1995 Ken Nakata
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FPU_EMULATE_H_
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#define _FPU_EMULATE_H_
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#include <sys/types.h>
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/*
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* Floating point emulator (tailored for SPARC/modified for m68k, but
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* structurally machine-independent).
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*
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* Floating point numbers are carried around internally in an `expanded'
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* or `unpacked' form consisting of:
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* - sign
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* - unbiased exponent
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* - mantissa (`1.' + 80-bit fraction + guard + round)
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* - sticky bit
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* Any implied `1' bit is inserted, giving a 81-bit mantissa that is
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* always nonzero. Additional low-order `guard' and `round' bits are
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* scrunched in, making the entire mantissa 83 bits long. This is divided
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* into three 32-bit words, with `spare' bits left over in the upper part
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* of the top word (the high bits of fp_mant[0]). An internal `exploded'
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* number is thus kept within the half-open interval [1.0,2.0) (but see
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* the `number classes' below). This holds even for denormalized numbers:
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* when we explode an external denorm, we normalize it, introducing low-order
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* zero bits, so that the rest of the code always sees normalized values.
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*
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* Note that a number of our algorithms use the `spare' bits at the top.
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* The most demanding algorithm---the one for sqrt---depends on two such
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* bits, so that it can represent values up to (but not including) 8.0,
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* and then it needs a carry on top of that, so that we need three `spares'.
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*
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* The sticky-word is 32 bits so that we can use `OR' operators to goosh
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* whole words from the mantissa into it.
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*
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* All operations are done in this internal extended precision. According
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* to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
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* it is OK to do a+b in extended precision and then round the result to
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* single precision---provided single, double, and extended precisions are
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* `far enough apart' (they always are), but we will try to avoid any such
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* extra work where possible.
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*/
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struct fpn {
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int fp_class; /* see below */
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int fp_sign; /* 0 => positive, 1 => negative */
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int fp_exp; /* exponent (unbiased) */
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int fp_sticky; /* nonzero bits lost at right end */
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u_int fp_mant[3]; /* 83-bit mantissa */
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};
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#define FP_NMANT 83 /* total bits in mantissa (incl g,r) */
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#define FP_NG 2 /* number of low-order guard bits */
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#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
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#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
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#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
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#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
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#define CPYFPN(dst, src) \
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if ((dst) != (src)) { \
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(dst)->fp_class = (src)->fp_class; \
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(dst)->fp_sign = (src)->fp_sign; \
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(dst)->fp_exp = (src)->fp_exp; \
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(dst)->fp_sticky = (src)->fp_sticky; \
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(dst)->fp_mant[0] = (src)->fp_mant[0]; \
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(dst)->fp_mant[1] = (src)->fp_mant[1]; \
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(dst)->fp_mant[2] = (src)->fp_mant[2]; \
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}
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/*
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* Number classes. Since zero, Inf, and NaN cannot be represented using
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* the above layout, we distinguish these from other numbers via a class.
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*/
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#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */
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#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */
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#define FPC_ZERO 0 /* zero (sign matters) */
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#define FPC_NUM 1 /* number (sign matters) */
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#define FPC_INF 2 /* infinity (sign matters) */
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#define ISNAN(fp) ((fp)->fp_class < 0)
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#define ISZERO(fp) ((fp)->fp_class == 0)
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#define ISINF(fp) ((fp)->fp_class == FPC_INF)
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/*
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* ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
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* to the `more significant' operand for our purposes. Appendix N says that
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* the result of a computation involving two numbers are:
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*
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* If both are SNaN: operand 2, converted to Quiet
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* If only one is SNaN: the SNaN operand, converted to Quiet
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* If both are QNaN: operand 2
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* If only one is QNaN: the QNaN operand
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*
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* In addition, in operations with an Inf operand, the result is usually
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* Inf. The class numbers are carefully arranged so that if
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* (unsigned)class(op1) > (unsigned)class(op2)
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* then op1 is the one we want; otherwise op2 is the one we want.
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*/
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#define ORDER(x, y) { \
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if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
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SWAP(x, y); \
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}
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#define SWAP(x, y) { \
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register struct fpn *swap; \
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swap = (x), (x) = (y), (y) = swap; \
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}
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/*
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* Emulator state.
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*/
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struct fpemu {
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struct frame *fe_frame; /* integer regs, etc */
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struct fpframe *fe_fpframe; /* FP registers, etc */
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u_int fe_fpsr; /* fpsr copy (modified during op) */
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u_int fe_fpcr; /* fpcr copy */
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struct fpn fe_f1; /* operand 1 */
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struct fpn fe_f2; /* operand 2, if required */
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struct fpn fe_f3; /* available storage for result */
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};
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/*****************************************************************************
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* End of definitions derived from Sparc FPE
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*****************************************************************************/
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/*
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* Internal info about a decoded effective address.
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*/
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struct insn_ea {
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int ea_regnum;
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int ea_ext[3]; /* extention words if any */
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int ea_flags; /* flags == 0 means mode 2: An@ */
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#define EA_DIRECT 0x001 /* mode [01]: Dn or An */
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#define EA_PREDECR 0x002 /* mode 4: An@- */
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#define EA_POSTINCR 0x004 /* mode 3: An@+ */
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#define EA_OFFSET 0x008 /* mode 5 or (7,2): APC@(d16) */
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#define EA_INDEXED 0x010 /* mode 6 or (7,3): APC@(Xn:*:*,d8) etc */
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#define EA_ABS 0x020 /* mode (7,[01]): abs */
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#define EA_PC_REL 0x040 /* mode (7,[23]): PC@(d16) etc */
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#define EA_IMMED 0x080 /* mode (7,4): #immed */
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#define EA_MEM_INDIR 0x100 /* mode 6 or (7,3): APC@(Xn:*:*,*)@(*) etc */
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#define EA_BASE_SUPPRSS 0x200 /* mode 6 or (7,3): base register suppressed */
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#define EA_FRAME_EA 0x400 /* MC68LC040 only: precalculated EA from
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format 4 stack frame */
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int ea_moffs; /* offset used for fmoveMulti */
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};
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#define ea_offset ea_ext[0] /* mode 5: offset word */
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#define ea_absaddr ea_ext[0] /* mode (7,[01]): absolute address */
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#define ea_immed ea_ext /* mode (7,4): immediate value */
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#define ea_basedisp ea_ext[0] /* mode 6: base displacement */
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#define ea_outerdisp ea_ext[1] /* mode 6: outer displacement */
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#define ea_idxreg ea_ext[2] /* mode 6: index register number */
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#define ea_fea ea_ext[0] /* MC68LC040 only: frame EA */
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struct instruction {
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u_int is_pc; /* insn's address */
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u_int is_nextpc; /* next PC */
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int is_advance; /* length of instruction */
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int is_datasize; /* size of memory operand */
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int is_opcode; /* opcode word */
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int is_word1; /* second word */
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struct insn_ea is_ea; /* decoded effective address mode */
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};
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/*
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* FP data types
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*/
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#define FTYPE_LNG 0 /* Long Word Integer */
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#define FTYPE_SNG 1 /* Single Prec */
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#define FTYPE_EXT 2 /* Extended Prec */
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#define FTYPE_BCD 3 /* Packed BCD */
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#define FTYPE_WRD 4 /* Word Integer */
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#define FTYPE_DBL 5 /* Double Prec */
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#define FTYPE_BYT 6 /* Byte Integer */
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/*
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* MC68881/68882 FPcr bit definitions (should these go to <m68k/reg.h>
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* or <m68k/fpu.h> or something?)
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*/
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/* fpsr */
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#define FPSR_CCB 0xff000000
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# define FPSR_NEG 0x08000000
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# define FPSR_ZERO 0x04000000
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# define FPSR_INF 0x02000000
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# define FPSR_NAN 0x01000000
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#define FPSR_QTT 0x00ff0000
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# define FPSR_QSG 0x00800000
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# define FPSR_QUO 0x007f0000
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#define FPSR_EXCP 0x0000ff00
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# define FPSR_BSUN 0x00008000
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# define FPSR_SNAN 0x00004000
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# define FPSR_OPERR 0x00002000
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# define FPSR_OVFL 0x00001000
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# define FPSR_UNFL 0x00000800
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# define FPSR_DZ 0x00000400
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# define FPSR_INEX2 0x00000200
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# define FPSR_INEX1 0x00000100
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#define FPSR_AEX 0x000000ff
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# define FPSR_AIOP 0x00000080
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# define FPSR_AOVFL 0x00000040
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# define FPSR_AUNFL 0x00000020
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# define FPSR_ADZ 0x00000010
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# define FPSR_AINEX 0x00000008
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/* fpcr */
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#define FPCR_EXCP FPSR_EXCP
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# define FPCR_BSUN FPSR_BSUN
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# define FPCR_SNAN FPSR_SNAN
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# define FPCR_OPERR FPSR_OPERR
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# define FPCR_OVFL FPSR_OVFL
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# define FPCR_UNFL FPSR_UNFL
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# define FPCR_DZ FPSR_DZ
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# define FPCR_INEX2 FPSR_INEX2
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# define FPCR_INEX1 FPSR_INEX1
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#define FPCR_MODE 0x000000ff
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# define FPCR_PREC 0x000000c0
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# define FPCR_EXTD 0x00000000
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# define FPCR_SNGL 0x00000040
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# define FPCR_DBL 0x00000080
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# define FPCR_ROUND 0x00000030
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# define FPCR_NEAR 0x00000000
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# define FPCR_ZERO 0x00000010
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# define FPCR_MINF 0x00000020
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# define FPCR_PINF 0x00000030
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/*
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* Other functions.
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*/
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/* Build a new Quiet NaN (sign=0, frac=all 1's). */
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struct fpn *fpu_newnan __P((struct fpemu *fe));
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/*
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* Shift a number right some number of bits, taking care of round/sticky.
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* Note that the result is probably not a well-formed number (it will lack
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* the normal 1-bit mant[0]&FP_1).
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*/
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int fpu_shr __P((struct fpn * fp, int shr));
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/*
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* Round a number according to the round mode in FPCR
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*/
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int fpu_round __P((register struct fpemu *fe, register struct fpn *fp));
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/* type conversion */
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void fpu_explode __P((struct fpemu *fe, struct fpn *fp, int t, u_int *src));
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void fpu_implode __P((struct fpemu *fe, struct fpn *fp, int t, u_int *dst));
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/*
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* non-static emulation functions
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*/
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/* type 0 */
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int fpu_emul_fmovecr __P((struct fpemu *fe, struct instruction *insn));
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int fpu_emul_fstore __P((struct fpemu *fe, struct instruction *insn));
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int fpu_emul_fscale __P((struct fpemu *fe, struct instruction *insn));
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/*
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* include function declarations of those which are called by fpu_emul_arith()
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*/
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#include "fpu_arith_proto.h"
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int fpu_emulate __P((struct frame *frame, struct fpframe *fpf));
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/*
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* "helper" functions
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*/
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/* return values from constant rom */
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struct fpn *fpu_const __P((struct fpn *fp, u_int offset));
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/* update exceptions and FPSR */
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int fpu_upd_excp __P((struct fpemu *fe));
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u_int fpu_upd_fpsr __P((struct fpemu *fe, struct fpn *fp));
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/* address mode decoder, and load/store */
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int fpu_decode_ea __P((struct frame *frame, struct instruction *insn,
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struct insn_ea *ea, int modreg));
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int fpu_load_ea __P((struct frame *frame, struct instruction *insn,
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struct insn_ea *ea, char *dst));
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int fpu_store_ea __P((struct frame *frame, struct instruction *insn,
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struct insn_ea *ea, char *src));
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/* fpu_subr.c */
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void fpu_norm __P((register struct fpn *fp));
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#if !defined(FPE_DEBUG)
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# define FPE_DEBUG 0
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#endif
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#endif /* _FPU_EMULATE_H_ */
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