8fe65bf226
1. read/write overflow to array size.
2. abnormal master addressing
PR: kern/23825 (splitted kern/{24227,24228,24229,24230,24231,24232})
Submitted by: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
102 lines
3.6 KiB
C
102 lines
3.6 KiB
C
/* $NetBSD: x1226reg.h,v 1.2 2004/02/04 12:03:07 shige Exp $ */
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/*
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* Copyright (c) 2003 Shigeyuki Fukushima.
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* All rights reserved.
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*
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* Written by Shigeyuki Fukushima for the NetBSD project.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Shigeyuki Fukushima.
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* 4. The name of Shigeyuki Fukushima may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY SHIGEYUKI FUKUSHIMA ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SHIGEYUKI FUKUSHIMA
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Xicor X1226 RTC registers
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*/
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#ifndef _DEV_I2C_X1226REG_H_
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#define _DEV_I2C_X1226REG_H_
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/*
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* Xicor X1226 RTC I2C Address:
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*
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* 110 1111
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*/
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#define X1226_ADDRMASK 0x7f
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#define X1226_ADDR 0x6f
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/* XICOR X1226 Device Identifier */
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#define X1226_DEVID_CCR 0x6f
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#define X1226_DEVID_EEPROM 0x57
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/* Watchdog RTC registers */
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#define X1226_REG_Y2K 0x37 /* bcd century (19/20) */
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#define X1226_REG_DW 0x36 /* bcd ay of week (0-6) */
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#define X1226_REG_YR 0x35 /* bcd year (0-99) */
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#define X1226_REG_MO 0x34 /* bcd onth (1-12) */
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#define X1226_REG_DT 0x33 /* bcd ay (1-31) */
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#define X1226_REG_HR 0x32 /* bcd our (0-23) */
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#define X1226_REG_MN 0x31 /* bcd inute (0-59) */
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#define X1226_REG_SC 0x30 /* bcd econd (0-59) */
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#define X1226_REG_RTC_BASE 0x30
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#define X1226_REG_RTC_SIZE ((X1226_REG_Y2K - X1226_REG_RTC_BASE) + 1)
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/* Watchdog RTC registers mask */
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#define X1226_REG_Y2K_MASK 0x39
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#define X1226_REG_DW_MASK 0x07
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#define X1226_REG_YR_MASK 0xff
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#define X1226_REG_MO_MASK 0x1f
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#define X1226_REG_DT_MASK 0x3f
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#define X1226_REG_HR12_MASK 0x1f
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#define X1226_REG_HR24_MASK 0x3f
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#define X1226_REG_MN_MASK 0x7f
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#define X1226_REG_SC_MASK 0x7f
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#define X1226_REG_SR 0x3f
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#define X1226_CTRL_DTR 0x13
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#define X1226_CTRL_ATR 0x12
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#define X1226_CTRL_INT 0x11
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#define X1226_CTRL_BL 0x10
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/* NVRAM size (512 x 8 bit) */
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#define X1226_NVRAM_START 0x0040
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#define X1226_NVRAM_END 0x00FF
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#define X1226_NVRAM_SIZE ((X1226_NVRAM_END - X1226_NVRAM_START) + 1)
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/* XICOR X1226 RTC flags */
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#define X1226_FLAG_SR_RTCF 0x01
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#define X1226_FLAG_SR_WEL 0x02
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#define X1226_FLAG_SR_RWEL 0x04
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#define X1226_FLAG_SR_AL0 0x20
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#define X1226_FLAG_SR_AL1 0x40
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#define X1226_FLAG_SR_BAT 0x80
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#define X1226_FLAG_HR_12HPM 0x20
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#define X1226_FLAG_HR_24H 0x80
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#endif /* _DEV_I2C_X1226REG_H_ */
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