dca6a7e025
immediately reasserted before we get a chance to process the interrupt, we can inadvertantly get stuck with zs_tx_stopped set. Move the delta detection to the hard zs interrupt handler; the softint handler will notice that something has happened with CTS and restart the transmitter if it's asserted.
174 lines
6.5 KiB
C
174 lines
6.5 KiB
C
/* $NetBSD: z8530sc.h,v 1.2 1996/10/15 06:57:43 scottr Exp $ */
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zsvar.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Clock source info structure
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*/
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struct zsclksrc {
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long clk; /* clock rate, in MHz, present on signal line */
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int flags; /* Specifies how this source can be used
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(RTxC divided, RTxC BRG, PCLK BRG, TRxC divided)
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and also if the source is "external" and if it
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is changeable (by an ioctl ex.). The
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source usage flags are used by the tty
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child. The other bits tell zsloadchannelregs
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if it should call an md signal source
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changing routine. ZSC_VARIABLE says if
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an ioctl should be able to cahnge the
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clock rate.*/
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};
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#define ZSC_PCLK 0x01
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#define ZSC_RTXBRG 0x02
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#define ZSC_RTXDIV 0x04
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#define ZSC_TRXDIV 0x08
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#define ZSC_VARIABLE 0x40
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#define ZSC_EXTERN 0x80
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#define ZSC_BRG 0x03
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#define ZSC_DIV 0x0c
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/*
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* Software state, per zs channel.
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*/
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struct zs_chanstate {
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/* Pointers to the device registers. */
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volatile u_char *cs_reg_csr; /* ctrl, status, and reg. number. */
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volatile u_char *cs_reg_data; /* data or numbered register */
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int cs_channel; /* sub-unit number */
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void *cs_private; /* sub-driver data pointer */
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struct zsops *cs_ops;
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int cs_defspeed; /* default baud rate (from PROM) */
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int cs_pclk_div16; /* PCLK / 16 used only by kbd & ms kids */
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int cs_clock_count; /* how many signal sources available */
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struct zsclksrc cs_clocks[4]; /* info on available signal sources */
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/*
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* We must keep a copy of the write registers as they are
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* mostly write-only and we sometimes need to set and clear
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* individual bits (e.g., in WR3). Not all of these are
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* needed but 16 bytes is cheap and this makes the addressing
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* simpler. Unfortunately, we can only write to some registers
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* when the chip is not actually transmitting, so whenever
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* we are expecting a `transmit done' interrupt the preg array
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* is allowed to `get ahead' of the current values. In a
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* few places we must change the current value of a register,
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* rather than (or in addition to) the pending value; for these
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* cs_creg[] contains the current value.
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*/
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u_char cs_creg[16]; /* current values */
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u_char cs_preg[16]; /* pending values */
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long cs_cclk_flag; /* flag for current clock source */
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long cs_pclk_flag; /* flag for pending clock source */
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int cs_csource; /* current source # */
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int cs_psource; /* pending source # */
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u_char cs_heldchange; /* change pending (creg != preg) */
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u_char cs_rr0; /* last rr0 processed */
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u_char cs_rr0_changes; /* rr0 changes noted in status int. */
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char cs_softreq; /* need soft interrupt call */
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char cs_chip; /* type of chip */
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char cs__spare;
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};
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#define ZS_ENHANCED_REG 8
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/* cs_Xreg which is used to hold WR7' data; reg 8 is an alias to the
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* data port, so we won't miss its loss. */
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/*
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* Function vector - per channel
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*/
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typedef void (*zsop_t)(register struct zs_chanstate *);
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struct zsops {
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zsop_t zsop_rxint; /* receive char available */
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zsop_t zsop_stint; /* external/status */
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zsop_t zsop_txint; /* xmit buffer empty */
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zsop_t zsop_softint; /* process software interrupt */
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};
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extern struct zsops zsops_null;
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struct zsc_softc {
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struct device zsc_dev; /* required first: base device */
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struct zs_chanstate zsc_cs[2]; /* channel A and B soft state */
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};
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struct zsc_attach_args {
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int channel; /* two serial channels per zsc */
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int hwflags;
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};
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#define ZS_HWFLAG_CONSOLE 1
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#define ZS_HWFLAG_CONABRT 2
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#define ZS_HWFLAG_RAW 4
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#define ZS_HWFLAG_IGCTS 16
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#define ZS_HWFLAG_IGDCD 32
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/* _CONSOLE says this port is the console, _CONABRT says a Break sequence acts as
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an abort, and _RAW recomends "raw" mode defaults on a tty.
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_CONABRT is turned off if an overly-long break is received.
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_IGCTS and _IGDCD tell the tty layer to ignore CTS or DCD. Assume
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whatever's least supprising (CTS and DCD present). Used mainly for
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external clock support on mac68k. The DCD and CTS pins are used also
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for clock inputs; not good for the UNIX I/O model! */
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#define ZS_CHIP_NMOS 0
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#define ZS_CHIP_CMOS 1
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#define ZS_CHIP_8580 2
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#define ZS_CHIP_ESCC 3
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void zs_loadchannelregs __P((struct zs_chanstate *));
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int zsc_intr_soft __P((void *));
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int zsc_intr_hard __P((void *));
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int zs_checkchip __P((struct zs_chanstate *));
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int zs_break __P((struct zs_chanstate *, int));
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int zs_getspeed __P((struct zs_chanstate *));
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void zs_iflush __P((struct zs_chanstate *));
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