b1f4ee5c2a
submitted by Denny Gentry <denny1@home.com>; investigation on the hardware done by Bob Nestor.
219 lines
6.7 KiB
C
219 lines
6.7 KiB
C
/* $NetBSD: if_snvar.h,v 1.10 1997/06/26 21:08:13 scottr Exp $ */
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/*
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* Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk)
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* You may use, copy, and modify this program so long as you retain the
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* copyright line.
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*/
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/*
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* if_snvar.h -- National Semiconductor DP8393X (SONIC) NetBSD/mac68k vars
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*/
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/*
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* Vendor types
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*/
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#define SN_VENDOR_UNKNOWN 0xff /* Unknown */
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#define SN_VENDOR_APPLE 0x00 /* Apple Computer/compatible */
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#define SN_VENDOR_DAYNA 0x01 /* Dayna/Kinetics EtherPort */
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#define SN_VENDOR_APPLE16 0x02 /* Apple Twisted Pair NB */
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/*
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* Memory access macros. Since we handle SONIC in 16 bit mode (PB5X0)
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* and 32 bit mode (everything else) using a single GENERIC kernel
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* binary, all structures have to be accessed using macros which can
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* adjust the offsets appropriately.
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*/
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#define SWO(m, a, o, x) (m ? (*(u_int32_t *)((u_int32_t *)(a) + (o)) = (x)) : \
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(*(u_int16_t *)((u_int16_t *)(a) + (o)) = (x)))
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#define SRO(m, a, o) (m ? (*(u_int32_t *)((u_int32_t *)(a) + (o)) & 0xffff) : \
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(*(u_int16_t *)((u_int16_t *)(a) + (o)) & 0xffff))
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/*
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* Register access macros. We use bus_space_* to talk to the Sonic
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* registers. A mapping table is used in case a particular configuration
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* hooked the regs up at non-word offsets.
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*/
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#define NIC_GET(sc, reg) (bus_space_read_2((sc)->sc_regt, \
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(sc)->sc_regh, \
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((sc)->sc_reg_map[(reg)])))
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#define NIC_PUT(sc, reg, val) (bus_space_write_2((sc)->sc_regt, \
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(sc)->sc_regh, \
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((sc)->sc_reg_map[reg]), \
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(val)))
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extern int kvtop(caddr_t addr);
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#define SONIC_GETDMA(p) (u_int32_t)(kvtop((caddr_t)(p)))
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#define SN_REGSIZE SN_NREGS*4
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/* mac68k does not have any write buffers to flush... */
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#define wbflush()
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/*
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* buffer sizes in 32 bit mode
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* 1 TXpkt is 4 hdr words + (3 * FRAGMAX) + 1 link word == 23 words == 92 bytes
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*
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* 1 RxPkt is 7 words == 28 bytes
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* 1 Rda is 4 words == 16 bytes
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*
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* The CDA is 17 words == 68 bytes
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*
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* total space in page 0 = NTDA * 92 + NRRA * 16 + NRDA * 28 + 68
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*/
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#define NRBA 8 /* # receive buffers < NRRA */
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#define RBAMASK (NRBA-1)
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#define NTDA 8 /* # transmit descriptors */
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#define NRRA 16 /* # receive resource descriptors */
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#define RRAMASK (NRRA-1) /* the reason why NRRA must be power of two */
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#define FCSSIZE 4 /* size of FCS appended to packets */
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/*
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* maximum receive packet size plus 2 byte pad to make each
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* one aligned. 4 byte slop (required for eobc)
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*/
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#define RBASIZE(sc) (sizeof(struct ether_header) + ETHERMTU + FCSSIZE + \
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((sc)->bitmode ? 6 : 2))
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/*
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* transmit buffer area
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*/
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#define TXBSIZE 1536 /* 6*2^8 -- the same size as the 8390 TXBUF */
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#define SN_NPAGES 2 + NRBA + (NTDA/2)
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typedef struct mtd {
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void *mtd_txp;
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u_int32_t mtd_vtxp;
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caddr_t mtd_buf;
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u_int32_t mtd_vbuf;
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struct mbuf *mtd_mbuf;
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} mtd_t;
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/*
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* The sn_softc for Mac68k if_sn.
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*/
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typedef struct sn_softc {
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struct device sc_dev;
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struct ethercom sc_ethercom;
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#define sc_if sc_ethercom.ec_if /* network visible interface */
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bus_space_tag_t sc_regt;
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bus_space_handle_t sc_regh;
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int bitmode; /* 32 bit mode == 1, 16 == 0 */
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bus_size_t sc_reg_map[SN_NREGS]; /* register offsets */
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u_int16_t snr_dcr; /* DCR for this instance */
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u_int16_t snr_dcr2; /* DCR2 for this instance */
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int slotno; /* Slot number */
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int sc_rramark; /* index into p_rra of wp */
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void *p_rra[NRRA]; /* RX resource descs */
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u_int32_t v_rra[NRRA]; /* DMA addresses of p_rra */
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u_int32_t v_rea; /* ptr to the end of the rra space */
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int sc_rxmark; /* current hw pos in rda ring */
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int sc_rdamark; /* current sw pos in rda ring */
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int sc_nrda; /* total number of RDAs */
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caddr_t p_rda;
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u_int32_t v_rda;
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caddr_t rbuf[NRBA];
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struct mtd mtda[NTDA];
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int mtd_hw; /* idx of first mtd given to hw */
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int mtd_prev; /* idx of last mtd given to hardware */
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int mtd_free; /* next free mtd to use */
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int mtd_tlinko; /*
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* offset of tlink of last txp given
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* to SONIC. Need to clear EOL on
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* this word to add a desc.
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*/
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int mtd_pint; /* Counter to set TXP_PINT */
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void *p_cda;
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u_int32_t v_cda;
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unsigned char *space;
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} sn_softc_t;
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/*
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* Accessing SONIC data structures and registers as 32 bit values
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* makes code endianess independent. The SONIC is however always in
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* bigendian mode so it is necessary to ensure that data structures shared
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* between the CPU and the SONIC are always in bigendian order.
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*/
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/*
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* Receive Resource Descriptor
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* This structure describes the buffers into which packets
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* will be received. Note that more than one packet may be
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* packed into a single buffer if constraints permit.
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*/
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#define RXRSRC_PTRLO 0 /* buffer address LO */
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#define RXRSRC_PTRHI 1 /* buffer address HI */
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#define RXRSRC_WCLO 2 /* buffer size (16bit words) LO */
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#define RXRSRC_WCHI 3 /* buffer size (16bit words) HI */
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#define RXRSRC_SIZE(sc) (sc->bitmode ? (4 * 4) : (4 * 2))
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/*
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* Receive Descriptor
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* This structure holds information about packets received.
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*/
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#define RXPKT_STATUS 0
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#define RXPKT_BYTEC 1
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#define RXPKT_PTRLO 2
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#define RXPKT_PTRHI 3
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#define RXPKT_SEQNO 4
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#define RXPKT_RLINK 5
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#define RXPKT_INUSE 6
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#define RXPKT_SIZE(sc) (sc->bitmode ? (7 * 4) : (7 * 2))
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#define RBASEQ(x) (((x)>>8)&0xff)
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#define PSNSEQ(x) ((x) & 0xff)
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/*
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* Transmit Descriptor
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* This structure holds information about packets to be transmitted.
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*/
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#define FRAGMAX 8 /* maximum number of fragments in a packet */
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#define TXP_STATUS 0 /* + transmitted packet status */
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#define TXP_CONFIG 1 /* transmission configuration */
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#define TXP_PKTSIZE 2 /* entire packet size in bytes */
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#define TXP_FRAGCNT 3 /* # fragments in packet */
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#define TXP_FRAGOFF 4 /* offset to first fragment */
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#define TXP_FRAGSIZE 3 /* size of each fragment desc */
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#define TXP_FPTRLO 0 /* ptr to packet fragment LO */
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#define TXP_FPTRHI 1 /* ptr to packet fragment HI */
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#define TXP_FSIZE 2 /* fragment size */
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#define TXP_WORDS TXP_FRAGOFF + (FRAGMAX*TXP_FRAGSIZE) + 1 /* 1 for tlink */
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#define TXP_SIZE(sc) ((sc->bitmode) ? (TXP_WORDS*4) : (TXP_WORDS*2))
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#define EOL 0x0001 /* end of list marker for link fields */
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/*
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* CDA, the CAM descriptor area. The SONIC has a 16 entry CAM to
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* match incoming addresses against. It is programmed via DMA
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* from a memory region.
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*/
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#define MAXCAM 16 /* number of user entries in CAM */
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#define CDA_CAMDESC 4 /* # words i na descriptor */
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#define CDA_CAMEP 0 /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
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#define CDA_CAMAP0 1 /* CAM Address Port 1 xx-xx-YY-YY-xx-xx */
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#define CDA_CAMAP1 2 /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
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#define CDA_CAMAP2 3
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#define CDA_ENABLE 64 /* mask enabling CAM entries */
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#define CDA_SIZE(sc) ((4*16 + 1) * ((sc->bitmode) ? 4 : 2))
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int snsetup __P((struct sn_softc *sc, u_int8_t *));
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void snintr __P((void *, int));
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void sn_get_enaddr __P((bus_space_tag_t t, bus_space_handle_t h,
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vm_offset_t o, u_char *dst));
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