131 lines
4.1 KiB
C
131 lines
4.1 KiB
C
/* $NetBSD: hdlgreg.h,v 1.2 2006/06/08 23:27:47 nonaka Exp $ */
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/*
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* Copyright (c) 2005, 2006 Kimihiro Nonaka
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _HDLGREG_H_
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#define _HDLGREG_H_
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/*
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* Memory map and register definitions for I-O DATA HDL-G
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*/
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/*
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* The memory map of I/O-DATA HDL-G looks like so:
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*
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* ------------------------------
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* Intel 80321 IOP Reserved
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* FFFF E900 ------------------------------
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* Peripheral Memory Mapped
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* Registers
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* FFFF E000 ------------------------------
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* On-board devices
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* FE80 0000 ------------------------------
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* SDRAM
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* A000 0000 ------------------------------
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* Reserved
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* 9100 0000 ------------------------------
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* Flash
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* 9080 0000 ------------------------------
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* Reserved
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* 9002 0000 ------------------------------
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* ATU Outbound Transaction
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* Windows
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* 8000 0000 ------------------------------
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* ATU Outbound Direct
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* Addressing Windows
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* 0000 1000 ------------------------------
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* Initialization Boot Code
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* from Flash
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* 0000 0000 ------------------------------
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*/
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/*
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* We allocate a page table for VA 0xfe400000 (4MB) and map the
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* PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
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*/
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#define HDLG_IOPXS_VBASE 0xfe400000UL
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#define HDLG_IOW_VBASE HDLG_IOPXS_VBASE
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#define HDLG_80321_VBASE (HDLG_IOW_VBASE + \
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VERDE_OUT_XLATE_IO_WIN_SIZE)
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/*
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* The GIGALANDISK on-board devices are mapped VA==PA during bootstrap.
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* Conveniently, the size of the on-board register space is 1 section
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* mapping.
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*/
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#define HDLG_OBIO_BASE 0xfe800000UL
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#define HDLG_OBIO_SIZE 0x00100000UL /* 1MB */
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#define HDLG_UART1 0xfe800000UL /* TI 16550 */
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#define HDLG_PLD 0xfe8d0000UL /* CPLD */
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/*
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* CPLD
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*/
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#define HDLG_LEDCTRL (HDLG_PLD + 0x00)
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#define LEDCTRL_STAT_GREEN 0x01
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#define LEDCTRL_STAT_RED 0x02
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#define LEDCTRL_USB1 0x04
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#define LEDCTRL_USB2 0x08
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#define LEDCTRL_USB3 0x10
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#define LEDCTRL_USB4 0x20
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#define LEDCTRL_HDD 0x40
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#define LEDCTRL_BUZZER 0x80
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#define HDLG_PWRLEDCTRL (HDLG_PLD + 0x01)
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#define PWRLEDCTRL_0 0x01
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#define PWRLEDCTRL_1 0x02
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#define PWRLEDCTRL_2 0x04
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#define PWRLEDCTRL_3 0x08
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#define HDLG_BTNSTAT (HDLG_PLD + 0x02)
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#define BTNSTAT_POWER 0x01
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#define BTNSTAT_SELECT 0x02
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#define BTNSTAT_COPY 0x04
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#define BTNSTAT_REMOVE 0x08
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#define BTNSTAT_RESET 0x10
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#define HDLG_INTEN (HDLG_PLD + 0x03)
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#define INTEN_PWRSW 0x01
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#define INTEN_BUTTON 0x02
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#define INTEN_RTC 0x40
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#define HDLG_PWRMNG (HDLG_PLD + 0x04)
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#define PWRMNG_POWOFF 0x01
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#define PWRMNG_RESET 0x02
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#define HDLG_FANCTRL (HDLG_PLD + 0x06)
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#define FANCTRL_OFF 0x00
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#define FANCTRL_ON 0x01
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#define hdlg_enable_pldintr(bit) \
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do { \
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*(volatile uint8_t *)HDLG_INTEN |= (bit); \
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} while (/*CONSTCOND*/0)
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#define hdlg_disable_pldintr(bit) \
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do { \
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*(volatile uint8_t *)HDLG_INTEN &= ~(bit); \
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} while (/*CONSTCOND*/0)
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#endif /* _HDLGREG_H_ */
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