1c10f508e4
And
+ Support LCD controller.
+ Support SMSC LAN 9117 Ethernet controller.
+ Comment outed 'options GXIO_DEFAULT_EXPANSION'. As for verdex-pro being
sold now, this option becomes obstructive.
+ Remove some usb devices in GUMSTIX.
+ Update GUMSTIX.
Also
Fix ARM ABI in gumstix_start.S. Thanks Brett Slager <bds at ifgd.net>.
Calculate RAM size in gumstix_start.S.
352 lines
10 KiB
C
352 lines
10 KiB
C
/* $NetBSD: gxpcic.c,v 1.11 2009/08/09 07:10:13 kiyohara Exp $ */
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/*
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* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
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* All rights reserved.
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*
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* Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM
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* Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the name of SOUM Corporation
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2002, 2003, 2005 Genetec corp. All rights reserved.
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*
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* PCMCIA/CF support for TWINTAIL (G4255EB)
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* Written by Hiroyuki Bessho for Genetec corp.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corp. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/callout.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <uvm/uvm.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pcmcia/pcmciareg.h>
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#include <dev/pcmcia/pcmciavar.h>
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#include <dev/pcmcia/pcmciachip.h>
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#include <arch/arm/xscale/pxa2x0cpu.h>
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#include <arch/arm/xscale/pxa2x0var.h>
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#include <arch/arm/xscale/pxa2x0reg.h>
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#include <arch/arm/xscale/pxa2x0_gpio.h>
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#include <arch/arm/xscale/pxa2x0_pcic.h>
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#include <arch/evbarm/gumstix/gumstixvar.h>
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#ifdef DEBUG
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#define DPRINTF(arg) printf arg
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#else
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#define DPRINTF(arg)
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#endif
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#define HAVE_CARD(r) (!((r) & GPIO_SET))
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static int gxpcic_match(device_t, cfdata_t, void *);
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static void gxpcic_attach(device_t, device_t, void *);
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static void gxpcic_socket_setup(struct pxapcic_socket *);
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static u_int gxpcic_read(struct pxapcic_socket *, int);
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static void gxpcic_write(struct pxapcic_socket *, int, u_int);
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static void gxpcic_set_power(struct pxapcic_socket *, int);
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static void gxpcic_clear_intr(struct pxapcic_socket *);
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static void *gxpcic_intr_establish(struct pxapcic_socket *, int,
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int (*)(void *), void *);
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static void gxpcic_intr_disestablish(struct pxapcic_socket *, void *);
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__inline void gxpcic_cpld_clk(void);
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__inline u_char gxpcic_cpld_read_bits(int bits);
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static int gxpcic_count_slot(struct pxapcic_softc *);
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CFATTACH_DECL_NEW(gxpcic, sizeof(struct pxapcic_softc),
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gxpcic_match, gxpcic_attach, NULL, NULL);
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static struct pxapcic_tag gxpcic_functions = {
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gxpcic_read,
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gxpcic_write,
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gxpcic_set_power,
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gxpcic_clear_intr,
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gxpcic_intr_establish,
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gxpcic_intr_disestablish,
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};
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static int
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gxpcic_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pxaip_attach_args *pxa = aux;
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struct pxa2x0_gpioconf *gpioconf;
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u_int reg;
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int i;
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if (strcmp(pxa->pxa_name, match->cf_name) != 0)
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return 0;
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/*
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* Check GPIO configuration. If you use these, it is sure already
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* to have been set by gxio.
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*/
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gpioconf = CPU_IS_PXA250 ? pxa25x_pcic_gpioconf :
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pxa27x_pcic_gpioconf;
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for (i = 0; gpioconf[i].pin != -1; i++) {
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reg = pxa2x0_gpio_get_function(gpioconf[i].pin);
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if (GPIO_FN(reg) != GPIO_FN(gpioconf[i].value) ||
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GPIO_FN_IS_OUT(reg) != GPIO_FN_IS_OUT(gpioconf[i].value)) {
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if (!CPU_IS_PXA250 && gpioconf[i].pin == 111)
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continue;
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return 0;
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}
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}
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return 1; /* match */
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}
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static void
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gxpcic_attach(device_t parent, device_t self, void *aux)
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{
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struct pxapcic_softc *sc = device_private(self);
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struct pxaip_attach_args *pxa = aux;
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int nslot, i;
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sc->sc_dev = self;
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sc->sc_iot = pxa->pxa_iot;
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nslot = gxpcic_count_slot(sc);
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for (i = 0; i < nslot; i++) {
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if (!gxpcic_slot_irqs[i].valid)
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continue;
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sc->sc_irqpin[i] = gxpcic_slot_irqs[i].prdy;
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sc->sc_irqcfpin[i] = gxpcic_slot_irqs[i].cd;
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}
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sc->sc_nslots = nslot;
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pxapcic_attach_common(sc, &gxpcic_socket_setup);
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}
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static void
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gxpcic_socket_setup(struct pxapcic_socket *so)
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{
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#if 0
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struct pxapcic_softc *sc = so->sc;
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#endif
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/* 3.3V only? */
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so->power_capability = PXAPCIC_POWER_3V;
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so->pcictag_cookie = NULL;
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so->pcictag = &gxpcic_functions;
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#if 0 /* We use already set values by u-boot. */
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bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh,
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MEMCTL_MCMEM(so->socket), MC_TIMING_VAL(9 ,9, 29));
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bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh,
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MEMCTL_MCATT(so->socket), MC_TIMING_VAL(9 ,9, 29));
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bus_space_write_4(sc->sc_iot, sc->sc_memctl_ioh,
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MEMCTL_MCIO(so->socket), MC_TIMING_VAL(5 ,5, 16));
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#endif
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}
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static u_int
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gxpcic_read(struct pxapcic_socket *so, int which)
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{
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int reg;
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switch (which) {
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case PXAPCIC_CARD_STATUS:
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reg = pxa2x0_gpio_get_function(gxpcic_slot_irqs[so->socket].cd);
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return (HAVE_CARD(reg) ?
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PXAPCIC_CARD_VALID : PXAPCIC_CARD_INVALID);
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case PXAPCIC_CARD_READY:
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reg = pxa2x0_gpio_get_function(
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gxpcic_slot_irqs[so->socket].prdy);
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return (reg & GPIO_SET ? 1 : 0);
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default:
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panic("%s: bogus register", __func__);
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}
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/* NOTREACHED */
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}
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/* ARGSUSED */
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static void
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gxpcic_write(struct pxapcic_socket *so, int which, u_int arg)
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{
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switch (which) {
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case PXAPCIC_CARD_POWER:
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case PXAPCIC_CARD_RESET:
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/* We can't */
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break;
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default:
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panic("%s: bogus register", __func__);
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}
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/* NOTREACHED */
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}
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static void
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gxpcic_set_power(struct pxapcic_socket *__so, int arg)
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{
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if(arg != PXAPCIC_POWER_OFF && arg != PXAPCIC_POWER_3V)
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panic("%s: bogus arg\n", __func__);
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/* 3.3V only? */
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}
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/* ARGSUSED */
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static void
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gxpcic_clear_intr(struct pxapcic_socket *so)
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{
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/* nothing to do */
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}
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static void *
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gxpcic_intr_establish(struct pxapcic_socket *so, int level,
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int (* ih_fun)(void *), void *ih_arg)
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{
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return pxa2x0_gpio_intr_establish(so->irqpin, IST_EDGE_FALLING,
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level, ih_fun, ih_arg);
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}
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/* ARGSUSED */
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static void
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gxpcic_intr_disestablish(struct pxapcic_socket *so, void *ih)
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{
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pxa2x0_gpio_intr_disestablish(ih);
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}
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/*
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* XXXXX: slot count functions from Linux
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*/
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__inline void
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gxpcic_cpld_clk(void)
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{
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pxa2x0_gpio_set_function(48, GPIO_OUT | GPIO_CLR);
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pxa2x0_gpio_set_function(48, GPIO_OUT | GPIO_SET);
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}
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__inline u_char
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gxpcic_cpld_read_bits(int bits)
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{
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u_int shift = 0, gpio;
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u_char result = 0;
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while (bits--) {
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gpio = pxa2x0_gpio_get_function(11);
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result |= ((gpio & GPIO_SET) == GPIO_SET) << shift;
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shift++;
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gxpcic_cpld_clk();
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}
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return result;
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}
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/*
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* We use the CPLD on the CF-CF card to read a value from a shift register.
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* If we can read that magic sequence, then we have 2 CF cards; otherwise
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* we assume just one. The CPLD will send the value of the shift register
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* on GPIO11 (the CD line for slot 0) when RESET is held in reset. We use
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* GPIO48 (nPWE) as a clock signal, GPIO52/53 (card enable for both cards)
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* to control read/write to the shift register.
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*/
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static int
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gxpcic_count_slot(struct pxapcic_softc *sc)
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{
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u_int poe, pce1, pce2;
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int nslot;
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poe = pxa2x0_gpio_get_function(48);
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pce1 = pxa2x0_gpio_get_function(52);
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pce2 = pxa2x0_gpio_get_function(53);
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/* RESET */
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pxa2x0_gpio_set_function(gxpcic_gpio_reset, GPIO_OUT | GPIO_CLR);
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/* Setup the shift register */
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pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_SET);
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pxa2x0_gpio_set_function(53, GPIO_OUT | GPIO_CLR);
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/* Tick the clock to program the shift register */
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gxpcic_cpld_clk();
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/* Now set shift register into read mode */
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pxa2x0_gpio_set_function(52, GPIO_OUT | GPIO_CLR);
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pxa2x0_gpio_set_function(53, GPIO_OUT | GPIO_SET);
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/* We can read the bits now -- 0xc2 means "Dual compact flash" */
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if (gxpcic_cpld_read_bits(8) != 0xc2)
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/* We do not have 2 CF slots */
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nslot = 1;
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else
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/* We have 2 CF slots */
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nslot = 2;
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delay(50);
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/* clear RESET */
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pxa2x0_gpio_set_function(gxpcic_gpio_reset, GPIO_OUT | GPIO_CLR);
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pxa2x0_gpio_set_function(48, poe);
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pxa2x0_gpio_set_function(52, pce1);
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pxa2x0_gpio_set_function(53, pce2);
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return nslot;
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}
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