02f0a2cf44
to deal with aliasing of regular memory pages, because many processors don't support it. Now, the pmap marks all mappings of a page that has any non-equivalent aliasing and any writable mapping, and the fault handlers watch for this and flush other mappings out of the TLB and cache before (re)entering a conflicting mapping. When a page has non-equivalent aliasing, only one writable mapping at a time may be in the TLB and cache. If no writable mapping is in the TLB and cache, any number of read-only mappings may be. The PA7100LC/PA7300LC fault handlers have not been converted yet.
72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
/* $NetBSD: pte.h,v 1.2 2002/08/11 22:29:09 fredette Exp $ */
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/* $OpenBSD: pte.h,v 1.8 2001/01/12 23:37:49 mickey Exp $ */
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/*
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* Copyright (c) 1990,1993,1994 The University of Utah and
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* the Computer Systems Laboratory at the University of Utah (CSL).
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* All rights reserved.
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*
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* Permission to use, copy, modify and distribute this software is hereby
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* granted provided that (1) source code retains these copyright, permission,
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* and disclaimer notices, and (2) redistributions including binaries
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* reproduce the notices in supporting documentation, and (3) all advertising
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* materials mentioning features or use of this software display the following
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* acknowledgement: ``This product includes software developed by the
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* Computer Systems Laboratory at the University of Utah.''
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*
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* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
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* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
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* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* CSL requests users of this software to return to csl-dist@cs.utah.edu any
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* improvements that they make and grant CSL redistribution rights.
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*
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* Utah $Hdr: pmap.h 1.24 94/12/14$
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* Author: Mike Hibler, Bob Wheeler, University of Utah CSL, 9/90
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*/
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#ifndef _HPPA_PTE_H_
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#define _HPPA_PTE_H_
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/* TLB access/protection values */
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#define TLB_REF 0x80000000 /* software/HPT only */
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#define TLB_NO_RW_ALIAS 0x40000000 /* software only */
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#define TLB_TRAP 0x20000000
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#define TLB_DIRTY 0x10000000
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#define TLB_BREAK 0x08000000
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#define TLB_AR_MASK 0x07f00000
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#define TLB_AR_NA 0x07300000
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#define TLB_AR_KR 0x00000000
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#define TLB_AR_KRW 0x01000000
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#define TLB_AR_KRX 0x02000000
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#define TLB_AR_KRWX 0x03000000
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#define TLB_AR_UR 0x00f00000
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#define TLB_AR_URW 0x01f00000
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#define TLB_AR_URX 0x02f00000
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#define TLB_AR_URWX 0x03f00000
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#define TLB_AR_WRITABLE(x) (((x) & 0x05000000) == 0x01000000)
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#define TLB_UNCACHEABLE 0x00080000
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#define TLB_UNMANAGED 0x00040000 /* software only */
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#define TLB_PID_MASK 0x0000fffe
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#define TLB_WIRED 0x00000001 /* software only */
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#define TLB_BITS "\020\024U\031W\032X\033N\034B\035D\036T\037A\040R"
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#define TLB_REF_POS 0
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#define TLB_NO_RW_ALIAS_POS 1
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#define TLB_TRAP_POS 2
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#define TLB_DIRTY_POS 3
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#define TLB_BREAK_POS 4
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#define TLB_UNCACHEABLE_POS 12
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#define TLB_UNMANAGED_POS 13
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#define TLB_WIRED_POS 31
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/* protection for a gateway page */
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#define TLB_GATE_PROT 0x04c00000
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/* protection for break page */
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#define TLB_BREAK_PROT 0x02c00000
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#endif /* _HPPA_PTE_H_ */
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