113 lines
4.5 KiB
C
113 lines
4.5 KiB
C
/* $NetBSD: psl.h,v 1.1 2002/06/05 01:04:23 fredette Exp $ */
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/* $OpenBSD: psl.h,v 1.6 1999/11/25 18:29:01 mickey Exp $ */
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/*
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* Copyright (c) 1999 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Michael Shalayeff.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPPA_PSL_H_
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#define _HPPA_PSL_H_
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/*
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* Rference:
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* 1. PA-RISC 1.1 Architecture and Instruction Set Manual
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* Hewlett Packard, 3rd Edition, February 1994; Part Number 09740-90039
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*/
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/*
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* Processor Status Word Bit Positions (in PA-RISC bit order)
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*/
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#define PSW_Y_POS (0)
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#define PSW_Z_POS (1)
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#define PSW_SS_POS (3) /* Reserved, Software-defined */
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#define PSW_E_POS (5)
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#define PSW_S_POS (6)
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#define PSW_T_POS (7)
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#define PSW_H_POS (8)
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#define PSW_L_POS (9)
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#define PSW_N_POS (10)
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#define PSW_X_POS (11)
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#define PSW_B_POS (12)
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#define PSW_C_POS (13)
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#define PSW_V_POS (14)
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#define PSW_M_POS (15)
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#define PSW_CB_POS (16)
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#define PSW_G_POS (25)
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#define PSW_F_POS (26)
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#define PSW_R_POS (27)
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#define PSW_Q_POS (28)
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#define PSW_P_POS (29)
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#define PSW_D_POS (30)
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#define PSW_I_POS (31)
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#define PSW_BITS "\020\001I\002D\003P\004Q\005R\006F\007G" \
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"\021M\022V\023C\024B\025X\026N\027L\030H" \
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"\031T\032S\033E\037Z\040Y"
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/*
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* Processor Status Word Bit Values
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*/
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#define PSW_Y (1 << (31-PSW_Y_POS)) /* Data Debug Trap Disable */
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#define PSW_Z (1 << (31-PSW_Z_POS)) /* Instruction Debug Trap Disable */
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#define PSW_SS (1 << (31-PSW_SS_POS)) /* Reserved; Software Single-Step */
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#define PSW_E (1 << (31-PSW_E_POS)) /* Little Endian Memory Access Enable */
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#define PSW_S (1 << (31-PSW_S_POS)) /* Secure Interval Timer */
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#define PSW_T (1 << (31-PSW_T_POS)) /* Taken Branch Trap Enable */
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#define PSW_H (1 << (31-PSW_H_POS)) /* Higher-privilege Transfer Trap Enable */
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#define PSW_L (1 << (31-PSW_L_POS)) /* Lower-privilege Transfer Trap Enable */
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#define PSW_N (1 << (31-PSW_N_POS)) /* Nullify */
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#define PSW_X (1 << (31-PSW_X_POS)) /* Data Memory Break Disable */
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#define PSW_B (1 << (31-PSW_B_POS)) /* Taken Branch */
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#define PSW_C (1 << (31-PSW_C_POS)) /* Instruction Address Translation Enable */
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#define PSW_V (1 << (31-PSW_V_POS)) /* Divide Step Correction */
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#define PSW_M (1 << (31-PSW_M_POS)) /* High-priority Machine Check Mask */
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#define PSW_CB (1 << (31-PSW_CB_POS)) /* Carry/Borrow Bits */
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#define PSW_G (1 << (31-PSW_G_POS)) /* Debug Trap Enable */
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#define PSW_F (1 << (31-PSW_F_POS)) /* Perfomance Monitor Interrupt Unmask */
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#define PSW_R (1 << (31-PSW_R_POS)) /* Recover Counter Enable */
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#define PSW_Q (1 << (31-PSW_Q_POS)) /* Interrupt State Collection Enable */
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#define PSW_P (1 << (31-PSW_P_POS)) /* Protection Identifier Validation Enable */
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#define PSW_D (1 << (31-PSW_D_POS)) /* Data Adress Translation Enable */
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#define PSW_I (1 << (31-PSW_I_POS)) /* External Interrupt, Power Failure
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Interrupt, and Low-Priority Machine
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Check Interrupt unmask */
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/*
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* Frequently Used PSW Values
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*/
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#define RESET_PSW (PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
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#ifdef _KERNEL
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#include <machine/intr.h>
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#endif
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#endif /* _HPPA_PSL_H_ */
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