196 lines
7.4 KiB
C
196 lines
7.4 KiB
C
/* $NetBSD: tcxreg.h,v 1.6 2014/07/16 17:58:35 macallan Exp $ */
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/*
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* differences between S24 and tcx, as far as this driver is concerned:
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* - S24 has 4MB VRAM, 24bit + 2bit control planes, no expansion possible
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* - tcx has 1MB VRAM, 8bit, no control planes, may have a VSIMM that bumps
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* VRAM to 2MB
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* - tcx can apply ROPs to STIP operations, unlike S24
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* - tcx has a Bt458 DAC, just like CG6. S24 has an AT&T 20C567
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* - the chip itself seems to be (almost) the same, just with different DACs
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* and VRAM configuration
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*/
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/*
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* A TCX is composed of numerous groups of control registers, all with TLAs:
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* DHC - ???
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* TEC - transform engine control?
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* THC - TEC Hardware Configuration
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* ROM - a 128Kbyte ROM with who knows what in it.
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* STIP - stipple engine, doesn't write attribute bits
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* RSTIP - stipple engine, writes attribute bits
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* BLIT - blit engine, doesn't copy attribute bits
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* RBLIT - blit engine, does copy attribute bits
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* ALT - ???
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* colormap - see below
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* frame buffer memory (video RAM)
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* possible other stuff
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*
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* RSTIP and RBLIT are set to size zero on my SS4's tcx, they work anyway
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* though. No sense using them since tcx has only the lower 8bit planes,
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* with no control planes, so there is no actual difference to STIP and
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* BLIT ops, and things like qemu and temlib may not actually implement
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* them.
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* The hardware cursor registers in the THC range are cut off by the size
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* attribute but seem to exist, although the parts that display the cursor
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* ( the DAC's overlay support ) only exist on the S24.
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* At this point I wouldn't be surprised if 8bit tcx actually supports
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* the DFB24 and RDFB32 ranges, with the upper planes returning garbage.
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*/
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#define TCX_REG_DFB8 0
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#define TCX_REG_DFB24 1
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#define TCX_REG_STIP 2
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#define TCX_REG_BLIT 3
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#define TCX_REG_RDFB32 4
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#define TCX_REG_RSTIP 5
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#define TCX_REG_RBLIT 6
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#define TCX_REG_TEC 7
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#define TCX_REG_CMAP 8
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#define TCX_REG_THC 9
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#define TCX_REG_ROM 10
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#define TCX_REG_DHC 11
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#define TCX_REG_ALT 12
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#define TCX_NREG 13
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/*
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* The S24 provides the framebuffer RAM mapped in three ways:
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* 26 bits used per pixel, in 32-bit words; the low-order 24 bits are
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* blue, green, and red values, and the other two bits select the
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* display modes, per pixel);
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* 24 bits per pixel, in 32-bit words; the high-order byte reads as
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* zero, and is ignored on writes (so the mode bits cannot be altered);
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* 8 bits per pixel, unpadded; writes to this space do not modify the
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* other 18 bits.
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*/
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#define TCX_CTL_8_MAPPED 0x00000000 /* 8 bits, uses color map */
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#define TCX_CTL_24_MAPPED 0x01000000 /* 24 bits, uses color map */
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#define TCX_CTL_24_LEVEL 0x03000000 /* 24 bits, ignores color map */
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#define TCX_CTL_PIXELMASK 0x00FFFFFF /* mask for index/level */
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/*
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* The DAC actually supports other bits, for example to select between the
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* red and green plane for 8bit output. Not useful here since we can only
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* access the red plane as 8bit framebuffer.
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*/
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/*
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* The layout of the THC.
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*/
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#define THC_CONFIG 0x00000000
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#define THC_SENSEBUS 0x00000080
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#define THC_DELAY 0x00000090
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#define THC_STRAPPING 0x00000094
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#define THC_LINECOUNTER 0x0000009c
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#define THC_HSYNC_START 0x000000a0
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#define THC_HSYNC_END 0x000000a4
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#define THC_HDISP_START 0x000000a8
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#define THC_HDISP_VSYNC 0x000000ac
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#define THC_HDISP_END 0x000000b0
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#define THC_MISC 0x00000818
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#define THC_CURSOR_POS 0x000008fc
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#define THC_CURSOR_1 0x00000900 /* bitmap bit 1 */
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#define THC_CURSOR_0 0x00000980 /* bitmap bit 0 */
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/* bits in thc_config ??? */
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#define THC_CFG_FBID 0xf0000000 /* id mask */
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#define THC_CFG_FBID_SHIFT 28
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#define THC_CFG_SENSE 0x07000000 /* sense mask */
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#define THC_CFG_SENSE_SHIFT 24
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#define THC_CFG_REV 0x00f00000 /* revision mask */
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#define THC_CFG_REV_SHIFT 20
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#define THC_CFG_RST 0x00008000 /* reset */
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/* bits in thc_hcmisc */
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#define THC_MISC_OPENFLG 0x80000000 /* open flag (what's that?) */
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#define THC_MISC_SWERR_EN 0x20000000 /* enable SW error interrupt */
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#define THC_MISC_VSYNC_LEVEL 0x08000000 /* vsync level when disabled */
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#define THC_MISC_HSYNC_LEVEL 0x04000000 /* hsync level when disabled */
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#define THC_MISC_VSYNC_DISABLE 0x02000000 /* vsync disable */
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#define THC_MISC_HSYNC_DISABLE 0x01000000 /* hsync disable */
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#define THC_MISC_XXX1 0x00ffe000 /* unused */
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#define THC_MISC_RESET 0x00001000 /* ??? */
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#define THC_MISC_XXX2 0x00000800 /* unused */
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#define THC_MISC_VIDEN 0x00000400 /* video enable */
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#define THC_MISC_SYNC 0x00000200 /* not sure what ... */
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#define THC_MISC_VSYNC 0x00000100 /* ... these really are */
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#define THC_MISC_SYNCEN 0x00000080 /* sync enable */
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#define THC_MISC_CURSRES 0x00000040 /* cursor resolution */
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#define THC_MISC_INTEN 0x00000020 /* v.retrace intr enable */
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#define THC_MISC_INTR 0x00000010 /* intr pending / ack bit */
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#define THC_MISC_DACWAIT 0x0000000f /* ??? */
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/*
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* Partial description of TEC.
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*/
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struct tcx_tec {
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u_int tec_config; /* what's in it? */
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u_int tec_xxx0[35];
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u_int tec_delay; /* */
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#define TEC_DELAY_SYNC 0x00000f00
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#define TEC_DELAY_WR_F 0x000000c0
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#define TEC_DELAY_WR_R 0x00000030
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#define TEC_DELAY_SOE_F 0x0000000c
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#define TEC_DELAY_SOE_S 0x00000003
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u_int tec_strapping; /* */
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#define TEC_STRAP_FIFO_LIMIT 0x00f00000
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#define TEC_STRAP_CACHE_EN 0x00010000
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#define TEC_STRAP_ZERO_OFFSET 0x00008000
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#define TEC_STRAP_REFRSH_DIS 0x00004000
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#define TEC_STRAP_REF_LOAD 0x00001000
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#define TEC_STRAP_REFRSH_PERIOD 0x000003ff
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u_int tec_hcmisc; /* */
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u_int tec_linecount; /* */
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u_int tec_hss; /* */
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u_int tec_hse; /* */
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u_int tec_hds; /* */
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u_int tec_hsedvs; /* */
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u_int tec_hde; /* */
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u_int tec_vss; /* */
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u_int tec_vse; /* */
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u_int tec_vds; /* */
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u_int tec_vde; /* */
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};
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/* DAC registers */
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#define DAC_ADDRESS 0x00000000
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#define DAC_FB_LUT 0x00000004 /* palette / gamma table */
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#define DAC_CONTROL_1 0x00000008
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#define DAC_CURSOR_LUT 0x0000000c /* cursor sprite colours */
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#define DAC_CONTROL_2 0x00000018
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#define DAC_C1_ID 0
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#define DAC_C1_REVISION 1
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#define DAC_C1_READ_MASK 4
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#define DAC_C1_BLINK_MASK 5
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#define DAC_C1_CONTROL_0 6
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