124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/* $NetBSD: tx39timerreg.h,v 1.5 2008/04/28 20:23:22 martin Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Toshiba TX3912/3922 Timer module
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*/
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#define TX39_TIMERRTCHI_REG 0x140
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#define TX39_TIMERRTCLO_REG 0x144
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#define TX39_TIMERALARMHI_REG 0x148
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#define TX39_TIMERALARMLO_REG 0x14C
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#define TX39_TIMERCONTROL_REG 0x150
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#define TX39_TIMERPERIODIC_REG 0x154
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/* Periodic timer (1.15MHz) */
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#ifdef TX391X
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/*
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* TX3912 base clock is 36.864MHz
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*/
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#define TX39_TIMERCLK 1152000
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#endif
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#ifdef TX392X
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/*
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* TX3922 base clock seems to be 32.25MHz (Telios)
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*/
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#define TX39_TIMERCLK 1007812
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#endif
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/* Real timer clock (32.768kHz) */
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#define TX39_RTCLOCK 32768
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#define TX39_MSEC2RTC(m) ((TX39_RTCLOCK * (m)) / 1000)
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/*
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* RTC Register High/Low
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*/
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/* R */
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#define TX39_TIMERRTCHI_SHIFT 0
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#ifdef TX391X
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#define TX39_TIMERRTCHI_MASK 0xff
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_TIMERRTCHI_MASK 0x7ff
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#endif /* TX392X */
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#define TX39_TIMERRTCHI(cr) ((cr) & TX39_TIMERRTCHI_MASK)
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/*
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* Alarm Register High/Low
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*/
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/* R/W */
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#ifdef TX391X /* 40bit */
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#define TX39_TIMERALARMHI_SHIFT 0
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#define TX39_TIMERALARMHI_MASK 0xff
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#endif /* TX391X */
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#ifdef TX392X /* 43bit */
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#define TX39_TIMERALARMHI_SHIFT 0
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#define TX39_TIMERALARMHI_MASK 0x7ff
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#endif /* TX392X */
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#define TX39_TIMERALARMHI(cr) ((cr) & TX39_TIMERALARMHI_MASK)
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/*
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* Timer Control Register
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*/
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#define TX39_TIMERCONTROL_FREEZEPRE 0x00000080
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#define TX39_TIMERCONTROL_FREEZERTC 0x00000040
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#define TX39_TIMERCONTROL_FREEZETIMER 0x00000020
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#define TX39_TIMERCONTROL_ENPERTIMER 0x00000010
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#define TX39_TIMERCONTROL_RTCCLR 0x00000008
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#define TX39_TIMERCONTROL_TESTCMS 0x00000004 /* Don't set */
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#define TX39_TIMERCONTROL_ENTESTCLK 0x00000002 /* Don't set */
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#define TX39_TIMERCONTROL_ENRTCTST 0x00000001
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/*
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* Periodic Timer Register
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*/
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/* R */
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#define TX39_TIMERPERIODIC_PERCNT_SHIFT 15
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#define TX39_TIMERPERIODIC_PERCNT_MASK 0xffff
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#define TX39_TIMERPERIODIC_PERCNT(cr) \
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(((cr) >> TX39_TIMERPERIODIC_PERCNT_SHIFT) & \
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TX39_TIMERPERIODIC_PERCNT_MASK)
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/* R/W */
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#define TX39_TIMERPERIODIC_PERVAL_SHIFT 0
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#define TX39_TIMERPERIODIC_PERVAL_MASK 0xffff
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#define TX39_TIMERPERIODIC_PERVAL(cr) \
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(((cr) >> TX39_TIMERPERIODIC_PERVAL_SHIFT) & \
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TX39_TIMERPERIODIC_PERVAL_MASK)
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#define TX39_TIMERPERIODIC_PERVAL_SET(cr, val) \
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((cr) | (((val) << TX39_TIMERPERIODIC_PERVAL_SHIFT) & \
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(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT)))
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#define TX39_TIMERPERIODIC_PERVAL_CLR(cr) ((cr) &= \
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~(TX39_TIMERPERIODIC_PERVAL_MASK << TX39_TIMERPERIODIC_PERVAL_SHIFT))
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#define TX39_TIMERPERIODIC_INTRRATE(val) \
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((val) + 1)/TX39_TIMERCLK /* unit:Hz */
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