307 lines
10 KiB
ArmAsm
307 lines
10 KiB
ArmAsm
/*
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* Machine dependent startup code for BEAGLEBOARD boards.
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* Based on omap_start.S
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*
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* Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec Corporation may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_omap.h"
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#include "opt_com.h"
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#include "opt_cpuoptions.h"
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#include "opt_cputypes.h"
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#include "opt_multiprocessor.h"
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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#include <arm/omap/omap2_obioreg.h>
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#include <evbarm/beagle/beagle.h>
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#ifdef CPU_CORTEXA9
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#include <arm/cortex/a9tmr_reg.h>
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#endif
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RCSID("$NetBSD: beagle_start.S,v 1.19 2014/03/29 14:47:30 matt Exp $")
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#if defined(VERBOSE_INIT_ARM)
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#define XPUTC(n) mov r0, n; bl xputc
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#define COM_MULT 4
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#define XPUTC_COM 1
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#else
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#define XPUTC(n)
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#endif
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#define INIT_MEMSIZE 128
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#define TEMP_L1_TABLE (0x80000000 + INIT_MEMSIZE * 0x100000 - L1_TABLE_SIZE)
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#if defined(CPU_CORTEXA9)
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#define MD_CPU_HATCH _C_LABEL(a9tmr_init_cpu_clock)
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#endif
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#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
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#define MD_CPU_HATCH _C_LABEL(gtmr_init_cpu_clock)
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#endif
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/*
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* Kernel start routine for BEAGLEBOARD boards.
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* At this point, this code has been loaded into SDRAM
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* and the MMU is off
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*/
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.section .start,"ax",%progbits
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.global _C_LABEL(beagle_start)
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_C_LABEL(beagle_start):
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/* Move into supervisor mode and disable IRQs/FIQs. */
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cpsid if, #PSR_SVC32_MODE
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/*
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* Save any arguments passed to us.
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*/
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movw r4, #:lower16:uboot_args
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movt r4, #:upper16:uboot_args
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stmia r4, {r0-r3}
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/*
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* bring the CPU into a known state (turn on SMP, caches, etc).
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*/
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bl cortex_init
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XPUTC(#67)
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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adr r1, .Lmmu_init_table
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bl arm_boot_l1pt_init
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XPUTC(#68)
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/*
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* Turn on the MMU, Caches, etc.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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bl arm_cpuinit
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XPUTC(#90)
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#ifdef MULTIPROCESSOR
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// Now spin up the second processors into the same state we are now.
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XPUTC(#77)
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XPUTC(#80)
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XPUTC(#60)
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// Make sure the contents of the data cache are in memory
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// for the secondary CPUs
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bl _C_LABEL(armv7_dcache_wbinv_all)
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bl omap_mpinit
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XPUTC(#62)
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#endif
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XPUTC(#13)
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XPUTC(#10)
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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*/
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b start /* Jump to start (flushes pipeline). */
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nop
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nop
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nop
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nop
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/* NOTREACHED */
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#include <arm/cortex/a9_mpsubr.S>
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#ifdef MULTIPROCESSOR
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omap_mpinit:
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mrc p15, 0, r0, c0, c0, 5 // MPIDR read
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ubfx r1, r0, #30, #2 // get top 2 bits
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cmp r1, #2 // =2?
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bxne lr // no, not MP
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movw r3, #:lower16:OMAP4_WUGEN_BASE
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movt r3, #:upper16:OMAP4_WUGEN_BASE
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// First we setup the address for the secondaries to jump to.
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adr r0, cortex_mpstart
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str r0, [r3, #OMAP4_AUX_CORE_BOOT1]
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dsb
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// tell the secondary boot rom(s) to exit their loop
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ldr r1, [r3, #OMAP4_AUX_CORE_BOOT0] // load AUX_CORE_BOOT_0
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orr r1, r1, #0xf0 // add mask for cpu #1
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str r1, [r3, #OMAP4_AUX_CORE_BOOT0] // store AUX_CORE_BOOT_0
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dsb
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// Now we kick it and return.
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sev
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movw r3, #:lower16:arm_cpu_hatched
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movt r3, #:upper16:arm_cpu_hatched
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// Let's wait for the secondary to hatch.
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mov r1, #0x1000000
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1: dmb
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ldr r0, [r3]
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cmp r0, #0
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bxne lr
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subs r1, r1, #1
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bne 1b
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XPUTC(#84)
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bx lr
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END(omap_mpinit)
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#endif
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.Lmmu_init_table:
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/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE, KERNEL_BASE,
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(INIT_MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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#ifdef MULTIPROCESSOR
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L1_S_V6_S |
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#endif
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_B | L1_S_C)
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/* Map first 1MB of L4 CORE (so console will work) */
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MMU_INIT(OMAP_L4_CORE_VBASE, OMAP_L4_CORE_BASE,
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(OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#if OMAP_L4_CORE_BASE <= CONSADDR \
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&& CONSADDR < OMAP_L4_CORE_BASE + OMAP_L4_CORE_SIZE
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/* Map first 1MB of L4 CORE 1:1 (so console will work) */
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MMU_INIT(OMAP_L4_CORE_BASE, OMAP_L4_CORE_BASE,
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(OMAP_L4_CORE_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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/* Map first 4MB of L4 PERIPHERAL (so console will work) */
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MMU_INIT(OMAP_L4_PERIPHERAL_VBASE, OMAP_L4_PERIPHERAL_BASE,
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(OMAP_L4_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#if OMAP_L4_PERIPHERAL_BASE <= CONSADDR \
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&& CONSADDR < OMAP_L4_PERIPHERAL_BASE + OMAP_L4_PERIPHERAL_SIZE
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/* Map first 1MB of L4 PERIPHERAL 1:1 (so console will work) */
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MMU_INIT(OMAP_L4_PERIPHERAL_BASE, OMAP_L4_PERIPHERAL_BASE,
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(OMAP_L4_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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#if defined(OMAP_L4_WAKEUP_BASE) && defined(OMAP_L4_WAKEUP_VBASE)
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/* Map all 4MB of L4 WAKEUP (so console will work) */
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MMU_INIT(OMAP_L4_WAKEUP_VBASE, OMAP_L4_WAKEUP_BASE,
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(OMAP_L4_WAKEUP_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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#ifdef OMAP_L4_FAST_BASE
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/* Map first 1MB of L4 FAST (so console will work) */
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MMU_INIT(OMAP_L4_FAST_VBASE, OMAP_L4_FAST_BASE,
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(OMAP_L4_FAST_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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#ifdef OMAP_EMIF1_BASE
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/* Map first 1MB of EMIF1 (so we can probe memory size) */
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MMU_INIT(OMAP_EMIF1_VBASE, OMAP_EMIF1_BASE,
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(OMAP_EMIF1_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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#ifdef OMAP_EMIF2_BASE
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/* Map first 1MB of EMIF2 (so we can probe memory size) */
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MMU_INIT(OMAP_EMIF2_VBASE, OMAP_EMIF2_BASE,
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(OMAP_EMIF2_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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#ifdef OMAP_SDRC_BASE
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/* Map 64KB SDRAM Controller (SDRC) */
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MMU_INIT(OMAP_SDRC_VBASE, OMAP_SDRC_BASE,
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(OMAP_SDRC_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_APv7_KRW | L1_S_V6_XN)
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#endif
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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END(_C_LABEL(beagle_start))
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