82 lines
3.2 KiB
C
82 lines
3.2 KiB
C
/* $NetBSD: acia.h,v 1.4 2009/10/20 19:10:11 snj Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_ACIA_H
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#define _MACHINE_ACIA_H
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/*
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* Atari ST hardware:
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* Motorola 6850 Asynchronous Communications Interface Adapter
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*/
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#define KBD (((struct acia *)AD_ACIA))
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#define MDI (((struct acia *)AD_ACIA) + 1)
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struct acia {
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volatile u_char acb[4]; /* use only the even bytes */
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};
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#define ac_cs acb[0] /* control and status register */
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#define ac_da acb[2] /* data register */
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/* bits in control register: */
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/* 0x03 *//* clock divider */
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#define A_Q01 0x00 /* don't divide */
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#define A_Q16 0x01 /* divide by 16 */
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#define A_Q64 0x02 /* divide by 64 */
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#define A_RESET 0x03 /* master reset */
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/* 0x1C *//* word select bits */
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#define A_72E 0x00 /* 7 data, 2 stop, parity even */
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#define A_72O 0x04 /* 7 data, 2 stop, parity odd */
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#define A_71E 0x08 /* 7 data, 1 stop, parity even */
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#define A_71O 0x0C /* 7 data, 1 stop, parity odd */
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#define A_82N 0x10 /* 8 data, 2 stop, no parity */
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#define A_81N 0x14 /* 8 data, 1 stop, no parity */
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#define A_81E 0x18 /* 8 data, 1 stop, parity even */
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#define A_81O 0x1C /* 8 data, 1 stop, parity odd */
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/* 0x60 *//* RTS Low/High, TXINT en/dis, BREAK */
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#define A_TXPOL 0x00 /* RTS Low, TXINT disabled */
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#define A_TXINT 0x20 /* RTS Low, TXINT enabled */
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#define A_TXOFF 0x40 /* RTS High, TXINT disabled */
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#define A_BREAK 0x60 /* RTS Low, TXINT disabled, BREAK */
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#define A_RXINT 0x80 /* enable receiver interrupt */
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/* bits in status register: */
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#define A_RXRDY 0x01 /* receiver ready */
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#define A_TXRDY 0x02 /* transmitter ready */
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#define A_CLOST 0x04 /* Carrier Lost */
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#define A_CTS 0x08 /* Clear To Send */
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#define A_FE 0x10 /* Frame Error */
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#define A_OE 0x20 /* Overrun Error */
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#define A_PE 0x40 /* Parity Error */
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#define A_IRQ 0x80 /* State of IRQ signal */
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/* values for the TT: */
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#define KBD_INIT (A_81N|A_Q64)
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#define MDI_INIT (A_81N|A_Q16)
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#endif /* _MACHINE_ACIA_H */
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