127 lines
3.7 KiB
C
127 lines
3.7 KiB
C
/* $NetBSD: ydsvar.h,v 1.7 2006/06/19 13:55:41 jmcneill Exp $ */
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/*
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* Copyright (c) 2000, 2001 Kazuki Sakamoto and Minoura Makoto.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_YDSVAR_H_
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#define _DEV_PCI_YDSVAR_H_
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#define N_PLAY_SLOTS 2 /* We use only 2 (R and L) */
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#define N_PLAY_SLOT_CTRL 2
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#define WORK_SIZE 0x0400
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/*
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* softc
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*/
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struct yds_dma {
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bus_dmamap_t map;
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caddr_t addr; /* VA */
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bus_dma_segment_t segs[1];
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int nsegs;
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size_t size;
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struct yds_dma *next;
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};
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struct yds_codec_softc {
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struct device sc_dev; /* base device */
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struct yds_softc *sc;
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int id;
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int status_data;
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int status_addr;
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struct ac97_host_if host_if;
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struct ac97_codec_if *codec_if;
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};
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struct yds_softc {
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struct device sc_dev; /* base device */
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pcitag;
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pcireg_t sc_id;
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int sc_revision;
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void *sc_ih; /* interrupt vectoring */
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bus_space_tag_t memt;
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bus_space_handle_t memh;
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bus_dma_tag_t sc_dmatag; /* DMA tag */
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u_int sc_flags;
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struct yds_codec_softc sc_codec[2]; /* Primary/Secondary AC97 */
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struct yds_dma *sc_dmas; /* List of DMA handles */
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/*
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* Play/record status
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*/
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struct {
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void (*intr)(void *); /* rint/pint */
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void *intr_arg; /* arg for intr */
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u_int offset; /* filled up to here */
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u_int blksize;
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u_int factor; /* byte per sample */
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u_int length; /* ring buffer length */
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struct yds_dma *dma; /* DMA handle for ring buf */
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} sc_play, sc_rec;
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/*
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* DSP control data
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*
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* Work space, play control data table, play slot control data,
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* rec slot control data and effect slot control data are
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* stored in a single memory segment in this order.
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*/
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struct yds_dma sc_ctrldata;
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/* KVA and offset in buffer of play ctrl data tbl */
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uint32_t *ptbl;
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off_t ptbloff;
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/* KVA and offset in buffer of rec slot ctrl data */
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struct rec_slot_ctrl_bank *rbank;
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off_t rbankoff;
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/* Array of KVA pointers and offset of play slot control data */
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struct play_slot_ctrl_bank *pbankp[N_PLAY_SLOT_CTRL_BANK
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*N_PLAY_SLOTS];
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off_t pbankoff;
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/*
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* Legacy support
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*/
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bus_space_tag_t sc_legacy_iot;
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bus_space_handle_t sc_opl_ioh;
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struct device *sc_mpu;
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bus_space_handle_t sc_mpu_ioh;
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struct audio_encoding_set *sc_encodings;
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/*
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* Power management
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*/
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struct pci_conf_state sc_pciconf;
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pcireg_t sc_dsctrl;
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pcireg_t sc_legacy;
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pcireg_t sc_ba[2];
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};
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#define sc_opl_iot sc_legacy_iot
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#define sc_mpu_iot sc_legacy_iot
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#endif /* _DEV_PCI_YDSVAR_H_ */
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