225 lines
6.4 KiB
C
225 lines
6.4 KiB
C
/* $NetBSD: s3c2800.c,v 1.7 2003/08/04 12:09:19 bsh Exp $ */
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/*
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2800.c,v 1.7 2003/08/04 12:09:19 bsh Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <arm/cpufunc.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/s3c2xx0/s3c2800reg.h>
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#include <arm/s3c2xx0/s3c2800var.h>
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#include "locators.h"
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#include "opt_cpuoptions.h"
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/* prototypes */
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static int s3c2800_match(struct device *, struct cfdata *, void *);
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static void s3c2800_attach(struct device *, struct device *, void *);
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static int s3c2800_search(struct device *, struct cfdata *, void *);
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/* attach structures */
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CFATTACH_DECL(ssio, sizeof(struct s3c2800_softc), s3c2800_match, s3c2800_attach,
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NULL, NULL);
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extern struct bus_space s3c2xx0_bs_tag;
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struct s3c2xx0_softc *s3c2xx0_softc;
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static int
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s3c2800_print(void *aux, const char *name)
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{
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struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *) aux;
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if (sa->sa_size)
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aprint_normal(" addr 0x%lx", sa->sa_addr);
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if (sa->sa_size > 1)
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aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1);
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if (sa->sa_intr != SSIOCF_INTR_DEFAULT)
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aprint_normal(" intr %d", sa->sa_intr);
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if (sa->sa_index != SSIOCF_INDEX_DEFAULT)
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aprint_normal(" unit %d", sa->sa_index);
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return (UNCONF);
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}
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int
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s3c2800_match(struct device *parent, struct cfdata *match, void *aux)
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{
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return 1;
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}
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void
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s3c2800_attach(struct device *parent, struct device *self, void *aux)
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{
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struct s3c2800_softc *sc = (struct s3c2800_softc *) self;
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bus_space_tag_t iot;
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const char *which_registers; /* for panic message */
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#define FAIL(which) do { \
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which_registers=(which); goto abort; }while(/*CONSTCOND*/0)
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s3c2xx0_softc = &(sc->sc_sx);
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sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
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if (bus_space_map(iot,
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S3C2800_INTCTL_BASE, S3C2800_INTCTL_SIZE,
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BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh))
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FAIL("intc");
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/* tell register addresses to interrupt handler */
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s3c2800_intr_init(sc);
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/* Map the GPIO registers */
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if (bus_space_map(iot, S3C2800_GPIO_BASE, S3C2800_GPIO_SIZE,
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0, &sc->sc_sx.sc_gpio_ioh))
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FAIL("GPIO");
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#if 0
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/* Map the DMA controller registers */
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if (bus_space_map(iot, S3C2800_DMAC_BASE, S3C2800_DMAC_SIZE,
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0, &sc->sc_sx.sc_dmach))
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FAIL("DMAC");
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#endif
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/* Memory controller */
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if (bus_space_map(iot, S3C2800_MEMCTL_BASE,
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S3C2800_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
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FAIL("MEMC");
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/* Clock manager */
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if (bus_space_map(iot, S3C2800_CLKMAN_BASE,
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S3C2800_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
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FAIL("CLK");
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#if 0
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/* Real time clock */
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if (bus_space_map(iot, S3C2800_RTC_BASE,
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S3C2800_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
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FAIL("RTC");
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#endif
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if (bus_space_map(iot, S3C2800_TIMER0_BASE,
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S3C2800_TIMER_SIZE, 0, &sc->sc_tmr0_ioh))
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FAIL("TIMER0");
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if (bus_space_map(iot, S3C2800_TIMER1_BASE,
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S3C2800_TIMER_SIZE, 0, &sc->sc_tmr1_ioh))
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FAIL("TIMER1");
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/* calculate current clock frequency */
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s3c2800_clock_freq(&sc->sc_sx);
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aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
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sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
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sc->sc_sx.sc_pclk / 1000000);
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aprint_naive("\n");
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/*
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* Attach devices.
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*/
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config_search(s3c2800_search, self, NULL);
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return;
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abort:
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panic("%s: unable to map %s registers",
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self->dv_xname, which_registers);
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#undef FAIL
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}
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int
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s3c2800_search(struct device * parent, struct cfdata * cf, void *aux)
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{
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struct s3c2800_softc *sc = (struct s3c2800_softc *) parent;
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struct s3c2xx0_attach_args aa;
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aa.sa_sc = sc;
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aa.sa_iot = sc->sc_sx.sc_iot;
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aa.sa_addr = cf->cf_loc[SSIOCF_ADDR];
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aa.sa_size = cf->cf_loc[SSIOCF_SIZE];
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aa.sa_index = cf->cf_loc[SSIOCF_INDEX];
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aa.sa_intr = cf->cf_loc[SSIOCF_INTR];
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if (config_match(parent, cf, &aa))
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config_attach(parent, cf, &aa, s3c2800_print);
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return 0;
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}
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/*
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* Issue software reset command.
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* called with MMU off.
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*/
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void
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s3c2800_softreset(void)
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{
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*(volatile unsigned int *)(S3C2800_CLKMAN_BASE + CLKMAN_SWRCON)
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= SWRCON_SWR;
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}
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/*
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* fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register.
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*/
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void
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s3c2800_clock_freq(struct s3c2xx0_softc *sc)
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{
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int mdiv, pdiv, sdiv;
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int pllcon, clkcon;
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pllcon = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh,
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CLKMAN_PLLCON);
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clkcon = bus_space_read_4(sc->sc_iot, sc->sc_clkman_ioh,
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CLKMAN_CLKCON);
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mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
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pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
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sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
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sc->sc_fclk = ((mdiv + 8) * S3C2XX0_XTAL_CLK) /
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((pdiv + 2) * (1 << sdiv));
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sc->sc_hclk = sc->sc_fclk;
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if (clkcon & CLKCON_HCLK)
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sc->sc_hclk /= 2;
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sc->sc_pclk = sc->sc_hclk;
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if (clkcon & CLKCON_PCLK)
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sc->sc_pclk /= 2;
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}
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