a1f833f3ae
Increase the delay between setting the command register and reading the status register. Reset the smbus controller if it has timed out. Tested on an IBM eServer x335.
79 lines
3.4 KiB
C
79 lines
3.4 KiB
C
/* $NetBSD: piixpmreg.h,v 1.5 2011/02/13 11:20:12 hannken Exp $ */
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/* $OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $ */
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/*
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* Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _DEV_PCI_PIIXREG_H_
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#define _DEV_PCI_PIIXREG_H_
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/*
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* Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions.
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*/
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/*
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* Power management registers.
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*/
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/* PCI configuration registers */
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#define PIIX_PM_BASE 0x40 /* Power management base address */
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#define PIIX_PM_BASE_CSB5_RESET 0x10 /* CSB5 PM reset */
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#define PIIX_DEVACTA 0x54 /* Device activity A (function 3) */
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#define PIIX_DEVACTB 0x58 /* Device activity B (function 3) */
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#define PIIX_PMREGMISC 0x80 /* Misc. Power management */
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#define PIIX_SMB_BASE 0x90 /* SMBus base address */
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#define PIIX_SMB_HOSTC 0xd0 /* SMBus host configuration */
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#define PIIX_SMB_HOSTC_HSTEN (1 << 16) /* enable host controller */
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#define PIIX_SMB_HOSTC_SMI (0 << 17) /* SMI */
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#define PIIX_SMB_HOSTC_IRQ (4 << 17) /* IRQ */
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#define PIIX_SMB_HOSTC_INTMASK (7 << 17)
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/* SMBus I/O registers */
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#define PIIX_SMB_HS 0x00 /* host status */
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#define PIIX_SMB_HS_BUSY (1 << 0) /* running a command */
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#define PIIX_SMB_HS_INTR (1 << 1) /* command completed */
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#define PIIX_SMB_HS_DEVERR (1 << 2) /* command error */
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#define PIIX_SMB_HS_BUSERR (1 << 3) /* transaction collision */
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#define PIIX_SMB_HS_FAILED (1 << 4) /* failed bus transaction */
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#define PIIX_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED"
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#define PIIX_SMB_HC 0x02 /* host control */
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#define PIIX_SMB_HC_INTREN (1 << 0) /* enable interrupts */
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#define PIIX_SMB_HC_KILL (1 << 1) /* kill current transaction */
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#define PIIX_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
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#define PIIX_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
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#define PIIX_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
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#define PIIX_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
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#define PIIX_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
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#define PIIX_SMB_HC_START (1 << 6) /* start transaction */
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#define PIIX_SMB_HCMD 0x03 /* host command */
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#define PIIX_SMB_TXSLVA 0x04 /* transmit slave address */
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#define PIIX_SMB_TXSLVA_READ (1 << 0) /* read direction */
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#define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
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#define PIIX_SMB_HD0 0x05 /* host data 0 */
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#define PIIX_SMB_HD1 0x06 /* host data 1 */
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#define PIIX_SMB_HBDB 0x07 /* host block data byte */
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#define PIIX_SMB_SC 0x08 /* slave control */
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#define PIIX_SMB_SC_ALERTEN (1 << 3) /* enable SMBALERT# */
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/* Power management I/O registers */
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#define PIIX_PM_PMTMR 0x08 /* power management timer */
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/* Misc */
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#define PIIX_PM_SIZE 0x38 /* Power management I/O space size */
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#define PIIX_SMB_SIZE 0x10 /* SMBus I/O space size */
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#endif /* !_DEV_PCI_PIIXREG_H_ */
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