81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/* $NetBSD: psl.h,v 1.2 1995/03/28 18:14:00 jtc Exp $ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Processor Status register definitions.
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*/
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#define PSL_U 0x08 /* PS<3> == 1 -> User mode */
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#define PSL_IPL 0x07 /* PS<2:0> -> Interrupt mask */
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/*
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* The interrupt priority levels.
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* Other IPL's are configured in software, and are listed below.
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*/
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#define PSL_IPL_0 0 /* all interrupts enabled */
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#define PSL_IPL_SOFT 1 /* block software interrupts */
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#define PSL_IPL_IO 4 /* block I/O device interrupts */
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#define PSL_IPL_CLOCK 5 /* block clock interrupts */
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#define PSL_IPL_HIGH 6 /* block everything except mchecks */
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/*
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* Miscellaneous PSL definitions
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*/
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#define PSL_MBZ (0xfffffffffffffff0) /* Must be always zero */
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#define PSL_USERSET (PSL_U) /* Must be set for user-mode */
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#define PSL_USERCLR (PSL_MBZ|PSL_IPL) /* Must be clr for user-mode */
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#define USERMODE(ps) ((ps & PSL_U) != 0) /* Is it user-mode? */
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#ifdef _KERNEL
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/*
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* Translation buffer invalidation macro definitions.
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*/
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#define TBI_A -2 /* Flush all TB entries */
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#define TBI_AP -1 /* Flush all per-process TB entries */
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#define TBI_SI 1 /* Invalidate ITB entry for va */
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#define TBI_SD 2 /* Invalidate DTB entry for va */
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#define TBI_S 3 /* Invalidate all entries for va */
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#define TBIA() pal_tbi(TBI_A, NULL)
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#define TBIAP() pal_tbi(TBI_AP, NULL)
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#define TBISI(va) pal_tbi(TBI_SI, va)
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#define TBISD(va) pal_tbi(TBI_SD, va)
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#define TBIS(va) pal_tbi(TBI_S, va)
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/*
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* Cache invalidation/flush routines.
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*/
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#define MB() alpha_mb() /* Flush all write buffers */
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#define IMB() pal_imb() /* Sync instruction cache w/data */
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void alpha_mb __P((void)); /* Flush all write buffers */
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void pal_imb __P((void)); /* Sync instruction cache */
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u_int64_t pal_swpipl __P((u_int64_t)); /* write new IPL, return old */
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void pal_tbi __P((u_int64_t, void *)); /* Invalidate TLB entries */
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#endif /* _KERNEL */
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