340 lines
9.8 KiB
C
340 lines
9.8 KiB
C
/* $NetBSD: ahareg.h,v 1.12 2005/12/11 12:21:25 christos Exp $ */
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/*-
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* Copyright (c) 1997-99 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Originally written by Julian Elischer (julian@tfs.com)
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* for TRW Financial Systems for use under the MACH(2.5) operating system.
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*
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* TRW Financial Systems, in accordance with their agreement with Carnegie
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* Mellon University, makes this software available to CMU to distribute
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* or use in any manner that they see fit as long as this message is kept with
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* the software. For this reason TFS also grants any other persons or
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* organisations permission to use or modify this software.
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*
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* TFS supplies this software to be publicly redistributed
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* on the understanding that TFS is not responsible for the correct
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* functioning of this software in any circumstances.
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*/
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typedef u_int8_t physaddr[3];
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typedef u_int8_t physlen[3];
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#define ltophys _lto3b
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#define phystol _3btol
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/*
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* I/O port offsets
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*/
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#define AHA_CTRL_PORT 0 /* control (wo) */
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#define AHA_STAT_PORT 0 /* status (ro) */
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#define AHA_CMD_PORT 1 /* command (wo) */
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#define AHA_DATA_PORT 1 /* data (ro) */
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#define AHA_INTR_PORT 2 /* interrupt status (ro) */
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/*
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* AHA_CTRL bits
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*/
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#define AHA_CTRL_HRST 0x80 /* Hardware reset */
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#define AHA_CTRL_SRST 0x40 /* Software reset */
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#define AHA_CTRL_IRST 0x20 /* Interrupt reset */
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#define AHA_CTRL_SCRST 0x10 /* SCSI bus reset */
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/*
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* AHA_STAT bits
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*/
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#define AHA_STAT_STST 0x80 /* Self test in Progress */
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#define AHA_STAT_DIAGF 0x40 /* Diagnostic Failure */
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#define AHA_STAT_INIT 0x20 /* Mbx Init required */
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#define AHA_STAT_IDLE 0x10 /* Host Adapter Idle */
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#define AHA_STAT_CDF 0x08 /* cmd/data out port full */
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#define AHA_STAT_DF 0x04 /* Data in port full */
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#define AHA_STAT_INVDCMD 0x01 /* Invalid command */
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/*
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* AHA_CMD opcodes
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*/
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#define AHA_NOP 0x00 /* No operation */
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#define AHA_MBX_INIT 0x01 /* Mbx initialization */
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#define AHA_START_SCSI 0x02 /* start scsi command */
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#define AHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */
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#define AHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */
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#if 0
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#define AHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */
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#define AHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */
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#define AHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */
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#define AHA_SPEED_SET 0x09 /* set transfer speed */
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#endif
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#define AHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */
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#define AHA_INQUIRE_CONFIG 0x0b /* return configuration data */
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#define AHA_TARGET_EN 0x0c /* enable target mode */
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#define AHA_INQUIRE_SETUP 0x0d /* return setup data */
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#define AHA_ECHO 0x1e /* Echo command data */
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#define AHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */
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#define AHA_EXT_BIOS 0x28 /* return extended bios info */
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#define AHA_MBX_ENABLE 0x29 /* enable mail box interface */
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/*
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* AHA_INTR bits
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*/
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#define AHA_INTR_ANYINTR 0x80 /* Any interrupt */
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#define AHA_INTR_SCRD 0x08 /* SCSI reset detected */
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#define AHA_INTR_HACC 0x04 /* Command complete */
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#define AHA_INTR_MBOA 0x02 /* MBX out empty */
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#define AHA_INTR_MBIF 0x01 /* MBX in full */
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/*
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* AHA Board IDs
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*/
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#define BOARD_1540_16HEAD_BIOS 0x00
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#define BOARD_1540_64HEAD_BIOS 0x30
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#define BOARD_1540 0x31
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#define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */
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#define BOARD_1640 0x42 /* aha-1640 */
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#define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */
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#define BOARD_1542C 0x44 /* aha-1542C */
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#define BOARD_1542CF 0x45 /* aha-1542CF */
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#define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */
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struct aha_mbx_out {
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u_char cmd;
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physaddr ccb_addr;
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};
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struct aha_mbx_in {
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u_char stat;
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physaddr ccb_addr;
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};
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/*
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* mbo.cmd values
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*/
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#define AHA_MBO_FREE 0x0 /* MBO entry is free */
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#define AHA_MBO_START 0x1 /* MBO activate entry */
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#define AHA_MBO_ABORT 0x2 /* MBO abort entry */
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/*
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* mbi.stat values
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*/
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#define AHA_MBI_FREE 0x0 /* MBI entry is free */
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#define AHA_MBI_OK 0x1 /* completed without error */
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#define AHA_MBI_ABORT 0x2 /* aborted ccb */
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#define AHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */
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#define AHA_MBI_ERROR 0x4 /* Completed with error */
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/* FOR OLD VERSIONS OF THE !%$@ this may have to be 16 (yuk) */
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#define AHA_NSEG 17 /* Number of scatter gather segments <= 16 */
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/* allow 64 K i/o (min) */
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struct aha_scat_gath {
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physlen seg_len;
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physaddr seg_addr;
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};
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struct aha_ccb {
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u_char opcode;
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u_char lun:3;
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u_char data_in:1; /* must be 0 */
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u_char data_out:1; /* must be 0 */
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u_char target:3;
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u_char scsi_cmd_length;
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u_char req_sense_length;
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physlen data_length;
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physaddr data_addr;
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physaddr link_addr;
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u_char link_id;
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u_char host_stat;
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u_char target_stat;
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u_char reserved[2];
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u_char scsi_cmd[12];
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struct scsi_sense_data scsi_sense;
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struct aha_scat_gath scat_gath[AHA_NSEG];
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/*----------------------------------------------------------------*/
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TAILQ_ENTRY(aha_ccb) chain;
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struct aha_ccb *nexthash;
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u_long hashkey;
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struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */
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int flags;
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#define CCB_ALLOC 0x01
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#define CCB_ABORT 0x02
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#ifdef AHADIAG
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#define CCB_SENDING 0x04
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#endif
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int timeout;
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/*
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* This DMA map maps the buffer involved in the transfer.
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* Its contents are loaded into "scat_gath" above.
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*/
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bus_dmamap_t dmamap_xfer;
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};
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/*
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* opcode fields
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*/
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#define AHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */
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#define AHA_TARGET_CCB 0x01 /* SCSI Target CCB */
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#define AHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scatter gather */
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#define AHA_RESET_CCB 0x81 /* SCSI Bus reset */
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/*
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* aha_ccb.host_stat values
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*/
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#define AHA_OK 0x00 /* cmd ok */
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#define AHA_LINK_OK 0x0a /* Link cmd ok */
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#define AHA_LINK_IT 0x0b /* Link cmd ok + int */
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#define AHA_SEL_TIMEOUT 0x11 /* Selection time out */
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#define AHA_OVER_UNDER 0x12 /* Data over/under run */
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#define AHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */
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#define AHA_INV_BUS 0x14 /* Invalid bus phase/sequence */
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#define AHA_BAD_MBO 0x15 /* Incorrect MBO cmd */
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#define AHA_BAD_CCB 0x16 /* Incorrect ccb opcode */
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#define AHA_BAD_LINK 0x17 /* Not same values of LUN for links */
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#define AHA_INV_TARGET 0x18 /* Invalid target direction */
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#define AHA_CCB_DUP 0x19 /* Duplicate CCB received */
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#define AHA_INV_CCB 0x1a /* Invalid CCB or segment list */
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struct aha_revision {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char boardid; /* type of board */
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/* 0x31 = AHA-1540 */
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/* 0x41 = AHA-1540A/1542A/1542B */
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/* 0x42 = AHA-1640 */
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/* 0x43 = AHA-1542C */
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/* 0x44 = AHA-1542CF */
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/* 0x45 = AHA-1542CF, BIOS v2.01 */
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/* 0x46 = AHA-1542CP */
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u_char spec_opts; /* special options ID */
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/* 0x41 = Board is standard model */
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u_char revision_1; /* firmware revision [0-9A-Z] */
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u_char revision_2; /* firmware revision [0-9A-Z] */
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} reply;
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};
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struct aha_extbios {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char flags; /* Bit 3 == 1 extended bios enabled */
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u_char mailboxlock; /* mail box lock code to unlock it */
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} reply;
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};
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struct aha_toggle {
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struct {
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u_char opcode;
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u_char enable;
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} cmd;
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};
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struct aha_config {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char chan;
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u_char intr;
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u_char scsi_dev:3;
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u_char :5;
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} reply;
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};
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struct aha_mailbox {
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struct {
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u_char opcode;
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u_char nmbx;
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physaddr addr;
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} cmd;
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};
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struct aha_unlock {
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struct {
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u_char opcode;
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u_char junk;
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u_char magic;
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} cmd;
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};
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struct aha_devices {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char lun_map[8];
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} reply;
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};
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struct aha_setup {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char sync_neg:1;
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u_char parity:1;
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u_char :6;
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u_char speed;
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u_char bus_on;
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u_char bus_off;
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u_char num_mbx;
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u_char mbx[3];
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struct {
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u_char offset:4;
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u_char period:3;
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u_char valid:1;
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} sync[8];
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u_char disc_sts;
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} reply;
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};
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#define INT9 0x01
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#define INT10 0x02
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#define INT11 0x04
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#define INT12 0x08
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#define INT14 0x20
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#define INT15 0x40
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#define EISADMA 0x00
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#define CHAN0 0x01
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#define CHAN5 0x20
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#define CHAN6 0x40
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#define CHAN7 0x80
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