26cf68556f
ATA subsystem was changed to support several outstanding commands, and use NCQ xfers if supported by both the controller and the disk, including NCQ error recovery. Set NCQ high priority for BPRIO_TIMECRITICAL xfers if supported. Added FUA support. Done some work towards MP-safe, all ATA code tsleep()/wakeup() replaced by condvars, and switched most code from spl* to mutexes (separate wd(4) and ata channel lock). Introduced new option WD_CHAOS_MONKEY to facilitate testing of error handling, fixed several uncovered issues. Also fixed several problems with kernel dump to wd(4) disk. Tested with ahcisata(4), mvsata(4), siisata(4), piixide(4) on amd64, with and without port multiplier, both disk and ATAPI devices; other drivers and archs mechanically adjusted and compile-tested. NCQ is supported for ahcisata(4) and siisata(4) for any controller, for mvsata(4) only Gen IIe ones for now. Also enabled ATAPI support in mvsata(4). Thanks to Matt Thomas for initial ATA infrastructure patch, and Jonathan A.Kollasch for siisata(4) NCQ changes and general testing. Also fixes PR kern/43169 (wd(4)); and PR kern/11811, PR kern/47041, PR kern/51979 (kernel dump)
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/* $NetBSD: efavar.h,v 1.3 2017/10/07 16:05:31 jdolecek Exp $ */
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/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Radoslaw Kujawa.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcvar.h>
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#define FATA1_CHANNELS 2
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#define PIO_COUNT 6
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struct efa_port {
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struct ata_channel chan;
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uint8_t mode; /* currently set mode */
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struct wdc_regs wdr[6]; /* PIO0-5 */
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bus_space_handle_t intst[6]; /* interrupt status register */
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bool mode_ok[6]; /* is this PIO mode usable? */
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};
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struct efa_softc {
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struct wdc_softc sc_wdcdev;
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struct ata_channel *sc_chanlist[FATA1_CHANNELS];
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struct efa_port sc_ports[FATA1_CHANNELS];
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/* Force 32-bit data port, otherwise always use 16-bit */
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bool sc_32bit_io;
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/* Disable hw interrupt support (for FastATA 1200 older than Mk-III) */
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bool sc_no_intr;
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struct isr sc_isr;
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volatile u_char *sc_intreg;
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void *sc_fata_softintr;
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struct wdc_regs sc_gayle_wdc_regs;
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};
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