115 lines
3.9 KiB
C
115 lines
3.9 KiB
C
/* $NetBSD: fdreg.h,v 1.2 2003/08/07 16:29:55 agc Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fdreg.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* AT floppy controller registers and bitfields
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*/
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/* uses NEC765 controller */
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#include <dev/ic/nec765reg.h>
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#ifndef _LOCORE
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struct fdreg_77 {
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u_int8_t fd_statusA;
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u_int8_t fd_statusB;
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u_int8_t fd_dor; /* Digital Output Register (R/W) */
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u_int8_t fd_tdr; /* Tape Control Register (R/W) */
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u_int8_t fd_msr; /* Main Status Register (R) */
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#define fd_drs fd_msr /* Data Rate Select Register (W) */
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u_int8_t fd_fifo; /* Data (FIFO) register (R/W) */
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u_int8_t fd_reserved;
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u_int8_t fd_dir; /* Digital Input Register (R) */
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#define fd_ccr fd_dir /* Configuration Control (W) */
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};
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struct fdreg_72 {
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u_int8_t fd_msr; /* Main Status Register (R) */
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#if already_a_define
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#define fd_drs fd_msr /* Data Rate Select Register (W) */
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#endif
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u_int8_t fd_fifo; /* Data (FIFO) register (R/W) */
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};
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union fdreg {
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struct fdreg_72 fun72;
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struct fdreg_77 fun77;
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};
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#endif
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/* Data Select Register bits */
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#define DRS_RESET 0x80
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#define DRS_POWER 0x40
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#define DRS_PLL 0x20
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#define FDC_500KBPS 0x00 /* 500KBPS MFM drive transfer rate */
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#define FDC_300KBPS 0x01 /* 300KBPS MFM drive transfer rate */
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#define FDC_250KBPS 0x02 /* 250KBPS MFM drive transfer rate */
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#define FDC_125KBPS 0x03 /* 125KBPS FM drive transfer rate */
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/* Digital Output Register bits */
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#define FDO_FDSEL 0x03 /* floppy device select */
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#define FDO_FRST 0x04 /* floppy controller reset */
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#define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */
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#define FDO_MOEN(n) ((1 << n) * 0x10) /* motor enable */
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#define FDI_DCHG 0x80 /* diskette has been changed */
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/* XXX - find a place for these... */
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#define NE7CMD_CFG 0x13
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#define CFG_EIS 0x40
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#define CFG_EFIFO 0x20
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#define CFG_POLL 0x10
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#define CFG_THRHLD_MASK 0x0f
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#define NE7CMD_LOCK 0x14
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#define CFG_LOCK 0x80
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#define NE7CMD_MOTOR 0x0b
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#define MOTOR_ON 0x80
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#define NE7CMD_DUMPREG 0x0e
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#define NE7CMD_VERSION 0x10
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#define ST1_OVERRUN 0x10
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/* sun3x - Floppy Control Register bits */
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#define FCR_TC 0x01 /* terminal count reset */
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#define FCR_EJECT 0x02 /* eject floppy */
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#define FCR_MTRON 0x04 /* motor on */
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#define FCR_DSEL1 0x08 /* select drive 1 */
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#define FCR_DSEL0 0x10 /* select drive 0 */
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#define FCR_DSEL(drive) ((drive) ? FCR_DSEL1 : FCR_DSEL0)
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/* sun3x - Register offsets */
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#define FDC_FCR_OFFSET 0x400
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#define FDC_FVR_OFFSET 0x800
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