65 lines
2.8 KiB
C
65 lines
2.8 KiB
C
/* $NetBSD: vfpreg.h,v 1.1 2008/03/15 10:16:43 rearnsha Exp $ */
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/*
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* Copyright (c) 2008 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _VFPREG_H
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#define _VFPREG_H
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/* FPSID regsiter */
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#define VFP_FPSID_IMP_MSK 0xff000000 /* Implementer */
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#define VFP_FPSID_IMP_ARM 0x41000000 /* Implementer: ARM */
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#define VFP_FPSID_SW 0x00800000 /* VFP implemented in SW */
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#define VFP_FPSID_FMT_MSK 0x00600000 /* FLDMX/FSTMX Format */
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#define VFP_FPSID_FMT_1 0x00000000 /* Standard format 1 */
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#define VFP_FPSID_FMT_2 0x00200000 /* Standard format 2 */
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#define VFP_FPSID_FMT_WEIRD 0x00600000 /* Non-standard format */
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#define VFP_FPSID_SP 0x00100000 /* Only single precision */
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#define VFP_FPSID_ARCH_MSK 0x000f0000 /* Architecture */
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#define VFP_FPSID_ARCH_V1 0x00000000 /* Arch VFPv1 */
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#define VFP_FPSID_ARCH_V2 0x00010000 /* Arch VFPv2 */
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#define VFP_FPSID_PART_MSK 0x0000ff00 /* Part number */
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#define VFP_FPSID_PART_VFP10 0x00001000 /* VFP10 */
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#define VFP_FPSID_VAR_MSK 0x000000f0 /* Variant */
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#define VFP_FPSID_VAR_ARM10 0x000000a0 /* Variant ARM10 */
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#define VFP_FPSID_REV_MSK 0x0000000f /* Revision */
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#define VFP_FPEXC_EX 0x80000000 /* Exception status bit */
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#define VFP_FPEXC_EN 0x40000000 /* Enable bit */
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#define VFP_FPSCR_DN 0x02000000 /* Default NaN mode */
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#define VFP_FPSCR_FZ 0x01000000 /* Flush-to-zero mode */
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#define FPU_VFP10_ARM10E 0x410001a0 /* Really a VFPv2 part */
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#define FPU_VFP11_ARM11 0x410120b0
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#endif /* _VFPREG_H */
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