383 lines
11 KiB
C
383 lines
11 KiB
C
/* $NetBSD: gemini_gpio.c,v 1.2 2008/12/14 01:55:15 matt Exp $ */
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/* adapted from
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* $NetBSD: omap2_gpio.c,v 1.6 2008/11/19 06:26:27 matt Exp
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*/
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gemini_gpio.c,v 1.2 2008/12/14 01:55:15 matt Exp $");
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#define _INTR_PRIVATE
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#include "locators.h"
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#include "gpio.h"
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#include "geminigmac.h"
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#include "opt_gemini.h"
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#include <sys/param.h>
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#include <sys/evcnt.h>
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#include <sys/atomic.h>
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#include <uvm/uvm_extern.h>
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#include <machine/intr.h>
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#include <arm/cpu.h>
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#include <arm/armreg.h>
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#include <arm/cpufunc.h>
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#include <machine/bus.h>
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#include <arm/gemini/gemini_reg.h>
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#include <arm/gemini/gemini_obiovar.h>
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#include <arm/gemini/gemini_gpiovar.h>
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#include <arm/pic/picvar.h>
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#if NGPIO > 0
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#include <sys/gpio.h>
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#include <dev/gpio/gpiovar.h>
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#endif
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static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
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static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
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static int gpio_pic_find_pending_irqs(struct pic_softc *);
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static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *);
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const struct pic_ops gpio_pic_ops = {
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.pic_block_irqs = gpio_pic_block_irqs,
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.pic_unblock_irqs = gpio_pic_unblock_irqs,
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.pic_find_pending_irqs = gpio_pic_find_pending_irqs,
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.pic_establish_irq = gpio_pic_establish_irq,
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};
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struct gpio_softc {
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device_t gpio_dev;
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struct pic_softc gpio_pic;
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struct intrsource *gpio_is;
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bus_space_tag_t gpio_memt;
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bus_space_handle_t gpio_memh;
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uint32_t gpio_enable_mask;
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uint32_t gpio_edge_mask;
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uint32_t gpio_edge_falling_mask;
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uint32_t gpio_edge_rising_mask;
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uint32_t gpio_level_mask;
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uint32_t gpio_level_hi_mask;
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uint32_t gpio_level_lo_mask;
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uint32_t gpio_inuse_mask;
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#if NGPIO > 0
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struct gpio_chipset_tag gpio_chipset;
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gpio_pin_t gpio_pins[32];
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#endif
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};
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#define PIC_TO_SOFTC(pic) \
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((struct gpio_softc *)((char *)(pic) - \
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offsetof(struct gpio_softc, gpio_pic)))
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#define GPIO_READ(gpio, reg) \
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bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))
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#define GPIO_WRITE(gpio, reg, val) \
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bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))
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void
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gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
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{
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struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
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KASSERT(irq_base == 0);
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gpio->gpio_enable_mask |= irq_mask;
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/*
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* If this a level source, ack it now. If it's still asserted
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* it'll come back.
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*/
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, gpio->gpio_enable_mask);
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if (irq_mask & gpio->gpio_level_mask)
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRCLR,
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irq_mask & gpio->gpio_level_mask);
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}
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void
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gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
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{
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struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
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KASSERT(irq_base == 0);
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gpio->gpio_enable_mask &= ~irq_mask;
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, ~irq_mask);
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/*
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* If any of the sources are edge triggered, ack them now so
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* we won't lose them.
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*/
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if (irq_mask & gpio->gpio_edge_mask)
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRCLR,
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irq_mask & gpio->gpio_edge_mask);
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}
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int
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gpio_pic_find_pending_irqs(struct pic_softc *pic)
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{
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struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
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uint32_t pending;
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pending = GPIO_READ(gpio, GEMINI_GPIO_INTRMSKSTATE);
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KASSERT((pending & ~gpio->gpio_enable_mask) == 0);
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if (pending == 0)
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return 0;
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/*
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* Now find all the pending bits and mark them as pending.
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*/
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(void) pic_mark_pending_sources(&gpio->gpio_pic, 0, pending);
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return 1;
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}
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void
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gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
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{
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struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
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KASSERT(is->is_irq < 32);
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uint32_t irq_mask = __BIT(is->is_irq);
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uint32_t v;
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#if 0
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unsigned int i;
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struct intrsource *maybe_is;
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#endif
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/*
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* Make sure the irq isn't enabled and not asserting.
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*/
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gpio->gpio_enable_mask &= ~irq_mask;
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRENB, gpio->gpio_enable_mask);
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRCLR, irq_mask);
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/*
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* Convert the type to a gpio type and figure out which bits in what
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* register we have to tweak.
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*/
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gpio->gpio_edge_rising_mask &= ~irq_mask;
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gpio->gpio_edge_falling_mask &= ~irq_mask;
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gpio->gpio_level_hi_mask &= ~irq_mask;
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gpio->gpio_level_lo_mask &= ~irq_mask;
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switch (is->is_type) {
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case IST_LEVEL_LOW: gpio->gpio_level_lo_mask |= irq_mask; break;
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case IST_LEVEL_HIGH: gpio->gpio_level_hi_mask |= irq_mask; break;
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case IST_EDGE_FALLING: gpio->gpio_edge_falling_mask |= irq_mask; break;
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case IST_EDGE_RISING: gpio->gpio_edge_rising_mask |= irq_mask; break;
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case IST_EDGE_BOTH:
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gpio->gpio_edge_rising_mask |= irq_mask;
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gpio->gpio_edge_falling_mask |= irq_mask;
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break;
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default:
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panic("%s: unknown is_type %d\n", __FUNCTION__, is->is_type);
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}
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gpio->gpio_edge_mask =
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gpio->gpio_edge_rising_mask | gpio->gpio_edge_falling_mask;
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gpio->gpio_level_mask =
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gpio->gpio_level_hi_mask|gpio->gpio_level_lo_mask;
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gpio->gpio_inuse_mask |= irq_mask;
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/*
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* Set the interrupt type.
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*/
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRTRIG, gpio->gpio_level_mask);
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GPIO_WRITE(gpio, GEMINI_GPIO_INTREDGEBOTH,
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gpio->gpio_edge_rising_mask & gpio->gpio_edge_falling_mask);
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GPIO_WRITE(gpio, GEMINI_GPIO_INTRDIR,
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gpio->gpio_edge_falling_mask | gpio->gpio_level_lo_mask);
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/*
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* Mark it as input by clearning bit(s) in PINDIR reg
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*/
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v = GPIO_READ(gpio, GEMINI_GPIO_PINDIR);
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v &= ~irq_mask;
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GPIO_WRITE(gpio, GEMINI_GPIO_PINDIR, v);
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#if 0
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for (i = 0, maybe_is = NULL; i < 32; i++) {
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if ((is = pic->pic_sources[i]) != NULL) {
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if (maybe_is == NULL || is->is_ipl > maybe_is->is_ipl)
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maybe_is = is;
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}
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}
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if (maybe_is != NULL) {
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is = gpio->gpio_is;
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KASSERT(is != NULL);
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is->is_ipl = maybe_is->is_ipl;
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(*is->is_pic->pic_ops->pic_establish_irq)(is->is_pic, is);
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}
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#endif
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}
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static int gpio_match(device_t, cfdata_t, void *);
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static void gpio_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(geminigpio,
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sizeof(struct gpio_softc),
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gpio_match, gpio_attach,
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NULL, NULL);
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#if NGPIO > 0 || NGEMINIGMAC > 0
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int
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geminigpio_pin_read(void *arg, int pin)
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{
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struct gpio_softc * const gpio = device_private(arg);
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return (GPIO_READ(gpio, GEMINI_GPIO_DATAIN) >> pin) & 1;
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}
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void
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geminigpio_pin_write(void *arg, int pin, int value)
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{
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struct gpio_softc * const gpio = device_private(arg);
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uint32_t mask = 1 << pin;
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if (value)
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GPIO_WRITE(gpio, GEMINI_GPIO_DATASET, mask);
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else
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GPIO_WRITE(gpio, GEMINI_GPIO_DATACLR, mask);
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}
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void
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geminigpio_pin_ctl(void *arg, int pin, int flags)
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{
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struct gpio_softc * const gpio = device_private(arg);
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uint32_t mask = 1 << pin;
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uint32_t old, new;
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old = GPIO_READ(gpio, GEMINI_GPIO_PINDIR);
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new = old;
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switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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case GPIO_PIN_INPUT: new &= ~mask; break;
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case GPIO_PIN_OUTPUT: new |= mask; break;
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default: return;
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}
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if (old != new)
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GPIO_WRITE(gpio, GEMINI_GPIO_PINDIR, new);
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}
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static void
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gpio_defer(device_t self)
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{
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struct gpio_softc * const gpio = device_private(self);
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struct gpio_chipset_tag * const gp = &gpio->gpio_chipset;
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struct gpiobus_attach_args gba;
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gpio_pin_t *pins;
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uint32_t mask, dir, valueout, valuein;
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int pin;
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gp->gp_cookie = gpio->gpio_dev;
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gp->gp_pin_read = geminigpio_pin_read;
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gp->gp_pin_write = geminigpio_pin_write;
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gp->gp_pin_ctl = geminigpio_pin_ctl;
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gba.gba_gc = gp;
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gba.gba_pins = gpio->gpio_pins;
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gba.gba_npins = __arraycount(gpio->gpio_pins);
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dir = GPIO_READ(gpio, GEMINI_GPIO_PINDIR);
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valueout = GPIO_READ(gpio, GEMINI_GPIO_DATAOUT);
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valuein = GPIO_READ(gpio, GEMINI_GPIO_DATAIN);
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for (pin = 0, mask = 1, pins = gpio->gpio_pins;
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pin < 32; pin++, mask <<= 1, pins++) {
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pins->pin_num = pin;
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if (gpio->gpio_inuse_mask & mask)
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pins->pin_caps = GPIO_PIN_INPUT;
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else
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pins->pin_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT;
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pins->pin_flags =
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(dir & mask) ? GPIO_PIN_OUTPUT : GPIO_PIN_INPUT;
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pins->pin_state =
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(((dir & mask) ? valueout : valuein) & mask)
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? GPIO_PIN_HIGH
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: GPIO_PIN_LOW;
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}
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config_found_ia(self, "gpiobus", &gba, gpiobus_print);
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}
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#endif /* NGPIO > 0 */
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int
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gpio_match(device_t parent, cfdata_t cfdata, void *aux)
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{
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struct obio_attach_args *oa = aux;
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if (oa->obio_addr == GEMINI_GPIO0_BASE
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|| oa->obio_addr == GEMINI_GPIO1_BASE
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|| oa->obio_addr == GEMINI_GPIO2_BASE)
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return 1;
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return 0;
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}
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void
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gpio_attach(device_t parent, device_t self, void *aux)
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{
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struct obio_attach_args * const oa = aux;
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struct gpio_softc * const gpio = device_private(self);
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int error;
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if (oa->obio_intr == OBIOCF_INTR_DEFAULT)
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panic("\n%s: no intr assigned", device_xname(self));
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if (oa->obio_size == OBIOCF_SIZE_DEFAULT)
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oa->obio_size = GEMINI_GPIO_SIZE;
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gpio->gpio_dev = self;
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gpio->gpio_memt = oa->obio_iot;
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error = bus_space_map(oa->obio_iot, oa->obio_addr, oa->obio_size,
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0, &gpio->gpio_memh);
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if (error) {
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aprint_error(": failed to map register %#lx@%#lx: %d\n",
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oa->obio_size, oa->obio_addr, error);
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return;
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}
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if (oa->obio_intrbase != OBIOCF_INTRBASE_DEFAULT) {
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gpio->gpio_pic.pic_ops = &gpio_pic_ops;
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strlcpy(gpio->gpio_pic.pic_name, device_xname(self),
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sizeof(gpio->gpio_pic.pic_name));
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gpio->gpio_pic.pic_maxsources = 32;
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pic_add(&gpio->gpio_pic, oa->obio_intrbase);
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aprint_normal(": interrupts %d..%d",
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oa->obio_intrbase, oa->obio_intrbase + 31);
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gpio->gpio_is = intr_establish(oa->obio_intr,
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IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, &gpio->gpio_pic);
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KASSERT(gpio->gpio_is != NULL);
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aprint_normal(", intr %d", oa->obio_intr);
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}
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aprint_normal("\n");
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#if NGPIO > 0
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config_interrupts(self, gpio_defer);
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#endif
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}
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