291 lines
7.8 KiB
C
291 lines
7.8 KiB
C
/* $NetBSD: opti82c700.c,v 1.1 1999/11/17 01:21:20 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Support for the Opti 82c700 PCI-ISA bridge interrupt controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/pci/pci_intr_fixup.h>
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#include <i386/pci/opti82c700reg.h>
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int opti82c700_getclink __P((pciintr_icu_handle_t, int, int *));
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int opti82c700_get_intr __P((pciintr_icu_handle_t, int, int *));
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int opti82c700_set_intr __P((pciintr_icu_handle_t, int, int));
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int opti82c700_get_trigger __P((pciintr_icu_handle_t, int, int *));
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int opti82c700_set_trigger __P((pciintr_icu_handle_t, int, int));
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const struct pciintr_icu opti82c700_pci_icu = {
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opti82c700_getclink,
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opti82c700_get_intr,
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opti82c700_set_intr,
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opti82c700_get_trigger,
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opti82c700_set_trigger,
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};
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struct opti82c700_handle {
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pci_chipset_tag_t ph_pc;
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pcitag_t ph_tag;
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};
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int opti82c700_addr __P((int, int *, int *));
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int
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opti82c700_init(pc, iot, tag, ptagp, phandp)
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pci_chipset_tag_t pc;
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bus_space_tag_t iot;
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pcitag_t tag;
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pciintr_icu_tag_t *ptagp;
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pciintr_icu_handle_t *phandp;
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{
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struct opti82c700_handle *ph;
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ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT);
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if (ph == NULL)
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return (1);
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ph->ph_pc = pc;
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ph->ph_tag = tag;
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*ptagp = &opti82c700_pci_icu;
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*phandp = ph;
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return (0);
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}
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int
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opti82c700_addr(link, addrofs, ofs)
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int link, *addrofs, *ofs;
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{
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int regofs, src;
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regofs = FIRESTAR_PIR_REGOFS(link);
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src = FIRESTAR_PIR_SELECTSRC(link);
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switch (src) {
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case FIRESTAR_PIR_SELECT_NONE:
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return (1);
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case FIRESTAR_PIR_SELECT_IRQ:
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if (regofs < 0 || regofs > 7)
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return (1);
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*addrofs = FIRESTAR_CFG_INTR_IRQ + (regofs >> 2);
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*ofs = (regofs & 3) << 3;
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break;
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case FIRESTAR_PIR_SELECT_PIRQ:
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case FIRESTAR_PIR_SELECT_BRIDGE:
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if (regofs < 0 || regofs > 3)
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return (1);
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*addrofs = FIRESTAR_CFG_INTR_PIRQ;
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*ofs = regofs << 2;
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break;
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default:
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return (1);
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}
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return (0);
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}
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int
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opti82c700_getclink(v, link, clinkp)
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pciintr_icu_handle_t v;
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int link, *clinkp;
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{
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if (FIRESTAR_LEGAL_LINK(link)) {
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*clinkp = link;
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return (0);
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}
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return (1);
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}
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int
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opti82c700_get_intr(v, clink, irqp)
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pciintr_icu_handle_t v;
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int clink, *irqp;
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{
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struct opti82c700_handle *ph = v;
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pcireg_t reg;
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int val, addrofs, ofs;
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if (FIRESTAR_LEGAL_LINK(clink) == 0)
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return (1);
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if (opti82c700_addr(clink, &addrofs, &ofs))
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return (1);
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
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val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
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*irqp = (val == FIRESTAR_PIRQ_NONE) ? 0xff : val;
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return (0);
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}
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int
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opti82c700_set_intr(v, clink, irq)
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pciintr_icu_handle_t v;
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int clink, irq;
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{
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struct opti82c700_handle *ph = v;
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int addrofs, ofs;
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pcireg_t reg;
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if (FIRESTAR_LEGAL_LINK(clink) == 0 || FIRESTAR_LEGAL_IRQ(irq) == 0)
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return (1);
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if (opti82c700_addr(clink, &addrofs, &ofs))
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return (1);
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
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reg &= ~(FIRESTAR_CFG_PIRQ_MASK << ofs);
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reg |= (irq << ofs);
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pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
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return (0);
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}
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int
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opti82c700_get_trigger(v, irq, triggerp)
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pciintr_icu_handle_t v;
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int irq, *triggerp;
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{
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struct opti82c700_handle *ph = v;
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int i, val, addrofs, ofs;
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pcireg_t reg;
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if (FIRESTAR_LEGAL_IRQ(irq) == 0) {
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/* ISA IRQ? */
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*triggerp = IST_EDGE;
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return (0);
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}
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/*
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* Search PCIDV1 registers.
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*/
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for (i = 0; i < 8; i++) {
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opti82c700_addr(FIRESTAR_PIR_MAKELINK(FIRESTAR_PIR_SELECT_IRQ,
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i), &addrofs, &ofs);
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
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val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
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if (val != irq)
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continue;
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val = ((reg >> ofs) >> FIRESTAR_TRIGGER_SHIFT) &
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FIRESTAR_TRIGGER_MASK;
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*triggerp = val ? IST_LEVEL : IST_EDGE;
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return (0);
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}
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return (1);
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}
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int
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opti82c700_set_trigger(v, irq, trigger)
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pciintr_icu_handle_t v;
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int irq, trigger;
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{
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struct opti82c700_handle *ph = v;
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int i, val, addrofs, ofs;
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pcireg_t reg;
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if (FIRESTAR_LEGAL_IRQ(irq) == 0) {
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/* ISA IRQ? */
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return ((trigger != IST_LEVEL) ? 0 : 1);
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}
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/*
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* Search PCIDV1 registers.
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*/
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for (i = 0; i < 8; i++) {
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opti82c700_addr(FIRESTAR_PIR_MAKELINK(FIRESTAR_PIR_SELECT_IRQ,
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i), &addrofs, &ofs);
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
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val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
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if (val != irq)
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continue;
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if (trigger == IST_LEVEL)
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reg |= (FIRESTAR_TRIGGER_MASK <<
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(FIRESTAR_TRIGGER_SHIFT + ofs));
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else
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reg &= ~(FIRESTAR_TRIGGER_MASK <<
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(FIRESTAR_TRIGGER_SHIFT + ofs));
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pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
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return (0);
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}
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return (1);
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}
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