188 lines
7.8 KiB
C
188 lines
7.8 KiB
C
/* $NetBSD: mfp.h,v 1.5 2003/05/03 18:10:47 wiz Exp $ */
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Leo Weppelman.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_MFP_H
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#define _MACHINE_MFP_H
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/*
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* Atari TT hardware: MFP1/MFP2
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* Motorola 68901 Multi-Function Peripheral
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*/
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#define MFP ((struct mfp *)AD_MFP)
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#define MFP2 ((struct mfp *)AD_MFP2)
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#ifdef _MILANHW_
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#define __MR(n) (3 + (4 * n))
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#endif
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#ifdef _ATARIHW_
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#define __MR(n) (1 + (2 * n))
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#endif
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struct mfp {
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volatile u_char mfb[__MR(24)-1]; /* Sparse */
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};
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#define mf_gpip mfb[__MR(0) ] /* gen-purp I/O interrupt port */
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#define mf_aer mfb[__MR(1) ] /* active edge register */
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#define mf_ddr mfb[__MR(2) ] /* data direction register */
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#define mf_iera mfb[__MR(3) ] /* interrupt enable register A */
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#define mf_ierb mfb[__MR(4) ] /* interrupt enable register B */
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#define mf_ipra mfb[__MR(5) ] /* interrupt pending register A */
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#define mf_iprb mfb[__MR(6) ] /* interrupt pending register B */
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#define mf_isra mfb[__MR(7) ] /* interrupt in-service register A */
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#define mf_isrb mfb[__MR(8) ] /* interrupt in-service register B */
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#define mf_imra mfb[__MR(9) ] /* interrupt mask register A */
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#define mf_imrb mfb[__MR(10)] /* interrupt mask register B */
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#define mf_vr mfb[__MR(11)] /* vector register */
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#define mf_tacr mfb[__MR(12)] /* timer control register A */
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#define mf_tbcr mfb[__MR(13)] /* timer control register B */
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#define mf_tcdcr mfb[__MR(14)] /* timer control register C+D */
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#define mf_tadr mfb[__MR(15)] /* timer data register A */
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#define mf_tbdr mfb[__MR(16)] /* timer data register B */
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#define mf_tcdr mfb[__MR(17)] /* timer data register C */
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#define mf_tddr mfb[__MR(18)] /* timer data register D */
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#define mf_scr mfb[__MR(19)] /* synchronous character register */
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#define mf_ucr mfb[__MR(20)] /* USART control register */
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#define mf_rsr mfb[__MR(21)] /* receiver status register */
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#define mf_tsr mfb[__MR(22)] /* transmitter status register */
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#define mf_udr mfb[__MR(23)] /* USART data register */
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/* names of IO port bits: */
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#define IO_PBSY 0x01 /* Parallel Busy */
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#define IO_SDCD 0x02 /* Serial Data Carrier Detect */
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#define IO_SCTS 0x04 /* Serial Clear To Send */
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#define IO_ISA1 0x08 /* ISA slot1 [ Hades only ] */
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#define IO_AINT 0x10 /* ACIA interrupt (KB or MIDI) */
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#define IO_DINT 0x20 /* DMA interrupt (FDC or HDC) */
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#define IO_SRI 0x40 /* Serial Ring Indicator */
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#define IO_MONO 0x80 /* Monochrome Monitor Detect */
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#define IO_ISA2 0x80 /* ISA slot2 [ Hades only ] */
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/* names of interrupts in register A: MFP1 */
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#define IA_MONO 0x80 /* IO_MONO */
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#define IA_ISA2 0x80 /* IO_ISA2 */
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#define IA_SRI 0x40 /* IO_SRI */
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#define IA_TIMA 0x20 /* Timer A */
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#define IA_RRDY 0x10 /* Serial Receiver Ready(=Full) */
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#define IA_RERR 0x08 /* Serial Receiver Error */
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#define IA_TRDY 0x04 /* Serial Transmitter Ready(=Empty) */
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#define IA_TERR 0x02 /* Serial Transmitter Error */
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#define IA_TIMB 0x01 /* Timer B */
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/* names of interrupts in register A: MFP2 */
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#define IA_SCSI 0x80 /* SCSI-controller */
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#define IA_RTC 0x40 /* Real Time Clock */
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#define IA_TIMA2 0x20 /* Timer A */
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/* 0x10 *//* reserved */
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/* 0x08 *//* reserved */
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/* 0x04 *//* reserved */
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/* 0x02 *//* reserved */
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#define IA_TIMB2 0x01 /* Timer B */
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/* names of interrupts in register B: MFP1*/
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#define IB_DINT 0x80 /* IO_DINT: from DMA devices */
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#define IB_AINT 0x40 /* IO_AINT: from kbd or midi */
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#define IB_TIMC 0x20 /* Timer C */
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#define IB_TIMD 0x10 /* Timer D */
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#define IB_ISA1 0x08 /* ISA1 interrupt [ Hades only ] */
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#define IB_SCTS 0x04 /* IO_SCTS */
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#define IB_SDCD 0x02 /* IO_SDCD */
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#define IB_PBSY 0x01 /* IO_PBSY */
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/* names of interrupts in register B: MFP2*/
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#define IB_SCDM 0x80 /* SCSI-DMA */
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#define IB_DCHG 0x40 /* Diskette change */
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/* 0x20 *//* reserved */
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/* 0x10 *//* reserved */
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#define IB_RISB 0x80 /* Serial Ring indicator SCC port B */
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#define IB_DMSC 0x40 /* SCC-DMA */
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#define IB_J602_3 0x02 /* Pin 3 J602 */
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#define IB_J602_1 0x01 /* Pin 1 J602 */
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/* bits in VR: */
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#define V_S 0x08 /* software end-of-interrupt mode */
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#define V_V 0xF0 /* four high bits of vector */
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/* bits in TCR: */
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/* 0x07 *//* divider */
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#define T_STOP 0x00 /* don't count */
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#define T_Q004 0x01 /* divide by 4 */
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#define T_Q010 0x02 /* divide by 10 */
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#define T_Q016 0x03 /* divide by 16 */
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#define T_Q050 0x04 /* divide by 50 */
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#define T_Q064 0x05 /* divide by 64 */
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#define T_Q100 0x06 /* divide by 100 */
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#define T_Q200 0x07 /* divide by 200 */
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#define T_EXTI 0x08 /* use extern impulse */
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#define T_LOWO 0x10 /* force output low */
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/* bits in UCR: */
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/* 0x01 *//* not used */
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#define U_EVEN 0x02 /* even parity */
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#define U_PAR 0x04 /* use parity */
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/* 0x18 *//* sync/async and stop bits */
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#define U_SYNC 0x00 /* synchrone */
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#define U_ST1 0x08 /* async, 1 stop bit */
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#define U_ST1_5 0x10 /* async, 1.5 stop bit */
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#define U_ST2 0x18 /* async, 2 stop bits */
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/* 0x60 *//* number of data bits */
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#define U_D8 0x00 /* 8 data bits */
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#define U_D7 0x20 /* 7 data bits */
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#define U_D6 0x40 /* 6 data bits */
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#define U_D5 0x60 /* 5 data bits */
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#define U_Q16 0x80 /* divide clock by 16 */
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/* bits in RSR: */
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#define RS_ENA 0x01 /* Receiver Enable */
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#define RS_STRIP 0x02 /* Synchronous Strip Enable */
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#define RS_CIP 0x04 /* Character in Progress */
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#define RS_BREAK 0x08 /* Break Detected */
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#define RS_FE 0x10 /* Frame Error */
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#define RS_PE 0x20 /* Parity Error */
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#define RS_OE 0x40 /* Overrun Error */
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#define RS_FULL 0x80 /* Buffer Full */
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/* bits in TSR: */
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#define TS_ENA 0x01 /* Transmitter Enable */
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/* 0x06 *//* state of dead transmitter output */
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#define TS_TRI 0x00 /* Quiet Output Tristate */
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#define TS_LOW 0x02 /* Quiet Output Low */
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#define TS_HIGH 0x04 /* Quiet Output High */
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#define TS_BACK 0x06 /* Loop Back Mode */
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#define TS_BREAK 0x08 /* Break Detected */
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#define TS_EOT 0x10 /* End of Transmission */
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#define TS_TURN 0x20 /* Auto Turnaround */
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#define TS_UE 0x40 /* Underrun Error */
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#define TS_EMPTY 0x80 /* Buffer Empty */
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#endif /* _MACHINE_MFP_H */
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