nisimura 75ff38a27d - Fix an error in primary cache line size detection logic; when IC and/or DC
bit is 1, then line size is 32.  Otherwise, 16.
1998-12-04 10:32:08 +00:00
..
1998-12-04 00:17:49 +00:00
1998-12-03 11:05:18 +00:00
1998-12-04 00:17:49 +00:00
1998-11-29 16:20:13 +00:00