73 lines
2.9 KiB
C
73 lines
2.9 KiB
C
/* $NetBSD: sa1111_reg.h,v 1.1 2001/03/10 18:50:38 toshii Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Interrupt Controller */
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/* number of interrupt bits */
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#define SACCIC_LEN 55
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#define SACCIC_INTTEST0 0x1600
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#define SACCIC_INTTEST1 0x1604
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#define SACCIC_INTEN0 0x1608
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#define SACCIC_INTEN1 0x160C
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#define SACCIC_INTPOL0 0x1610
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#define SACCIC_INTPOL1 0x1614
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#define SACCIC_INTTSTSEL 0x1618
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#define SACCIC_INTSTATCLR0 0x161C
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#define SACCIC_INTSTATCLR1 0x1620
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#define SACCIC_INTSET0 0x1624
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#define SACCIC_INTSET1 0x1628
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#define SACCIC_WAKE_EN0 0x162C
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#define SACCIC_WAKE_EN1 0x1630
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#define SACCIC_WAKE_POL0 0x1634
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#define SACCIC_WAKE_POL1 0x1638
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/* GPIO registers */
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#define SACCGPIOA_DDR 0x1000 /* data direction */
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#define SACCGPIOA_DVR 0x1004 /* data value */
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#define SACCGPIOA_SDR 0x1008 /* sleep direction */
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#define SACCGPIOA_SSR 0x100C /* sleep state */
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#define SACCGPIOB_DDR 0x1010
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#define SACCGPIOB_DVR 0x1014
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#define SACCGPIOB_SDR 0x1018
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#define SACCGPIOB_SSR 0x101C
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#define SACCGPIOC_DDR 0x1020
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#define SACCGPIOC_DVR 0x1024
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#define SACCGPIOC_SDR 0x1028
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#define SACCGPIOC_SSR 0x102C
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