226 lines
6.4 KiB
C
226 lines
6.4 KiB
C
/* $NetBSD: rmixlvar.h,v 1.7 2014/03/11 08:19:45 mrg Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_RMI_RMIXLVAR_H_
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#define _MIPS_RMI_RMIXLVAR_H_
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#include <mips/cpu.h>
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#include <mips/locore.h>
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#include <mips/rmi/rmixl_firmware.h>
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#include <sys/bus.h>
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#include <dev/pci/pcivar.h>
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extern void rmixl_pcr_init_core(void);
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static inline bool
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cpu_rmixl(const struct pridtab *ct)
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{
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if (ct->cpu_cid == MIPS_PRID_CID_RMI)
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return true;
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return false;
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}
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static inline bool
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cpu_rmixlr(const struct pridtab *ct)
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{
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u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE;
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if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLR)
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return true;
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return false;
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}
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static inline bool
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cpu_rmixls(const struct pridtab *ct)
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{
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u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE;
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if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLS)
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return true;
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return false;
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}
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static inline bool
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cpu_rmixlp(const struct pridtab *ct)
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{
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u_int type = ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE;
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if (cpu_rmixl(ct) && type == CIDFL_RMI_TYPE_XLP)
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return true;
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return false;
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}
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static inline int
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cpu_rmixl_chip_type(const struct pridtab *ct)
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{
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return ct->cpu_cidflags & MIPS_CIDFL_RMI_TYPE;
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}
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typedef enum {
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PSB_TYPE_UNKNOWN=0,
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PSB_TYPE_RMI,
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PSB_TYPE_DELL,
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} rmixlfw_psb_type_t;
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static inline const char *
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rmixlfw_psb_type_name(rmixlfw_psb_type_t type)
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{
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switch(type) {
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case PSB_TYPE_UNKNOWN:
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return "unknown";
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case PSB_TYPE_RMI:
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return "RMI";
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case PSB_TYPE_DELL:
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return "DELL";
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default:
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return "undefined";
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}
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}
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struct rmixl_config {
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uint64_t rc_io_pbase;
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uint64_t rc_flash_pbase; /* FLASH_BAR */
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uint64_t rc_flash_mask; /* FLASH_BAR */
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bus_addr_t rc_pci_cfg_pbase;
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bus_size_t rc_pci_cfg_size;
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bus_addr_t rc_pci_ecfg_pbase;
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bus_size_t rc_pci_ecfg_size;
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bus_addr_t rc_pci_mem_pbase;
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bus_size_t rc_pci_mem_size;
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bus_addr_t rc_pci_io_pbase;
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bus_size_t rc_pci_io_size;
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struct mips_bus_space rc_obio_eb_memt; /* DEVIO -eb */
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struct mips_bus_space rc_obio_el_memt; /* DEVIO -el */
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struct mips_bus_space rc_iobus_memt; /* Peripherals IO Bus */
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struct mips_bus_space rc_pci_cfg_memt; /* PCI CFG */
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struct mips_bus_space rc_pci_ecfg_memt; /* PCI ECFG */
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struct mips_bus_space rc_pci_memt; /* PCI MEM */
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struct mips_bus_space rc_pci_iot; /* PCI IO */
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struct mips_bus_dma_tag rc_dma_tag;
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bus_dma_tag_t rc_64bit_dmat;
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bus_dma_tag_t rc_32bit_dmat;
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bus_dma_tag_t rc_29bit_dmat;
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struct extent *rc_phys_ex; /* Note: MB units */
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struct extent *rc_obio_eb_ex;
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struct extent *rc_obio_el_ex;
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struct extent *rc_iobus_ex;
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struct extent *rc_pci_cfg_ex;
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struct extent *rc_pci_ecfg_ex;
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struct extent *rc_pci_mem_ex;
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struct extent *rc_pci_io_ex;
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int rc_mallocsafe;
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rmixlfw_info_t rc_psb_info;
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rmixlfw_psb_type_t rc_psb_type;
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volatile struct rmixlfw_cpu_wakeup_info
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*rc_cpu_wakeup_info;
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const void *rc_cpu_wakeup_end;
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};
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extern struct rmixl_config rmixl_configuration;
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extern void rmixl_obio_eb_bus_mem_init(bus_space_tag_t, void *);
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extern void rmixl_obio_el_bus_mem_init(bus_space_tag_t, void *);
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extern void rmixl_iobus_bus_mem_init(bus_space_tag_t, void *);
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extern void rmixl_pci_cfg_bus_mem_init(bus_space_tag_t, void *);
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extern void rmixl_pci_ecfg_bus_mem_init(bus_space_tag_t, void *);
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extern void rmixl_pci_bus_mem_init(bus_space_tag_t, void *);
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extern void rmixl_pci_bus_io_init(bus_space_tag_t, void *);
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extern void rmixl_addr_error_init(void);
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extern int rmixl_addr_error_check(void);
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extern uint64_t rmixl_mfcr(u_int);
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extern void rmixl_mtcr(uint64_t, u_int);
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extern void rmixl_eirr_ack(uint64_t, uint64_t, uint64_t);
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/*
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* rmixl_cache_err_dis:
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* - disable Cache, Data ECC, Snoop Tag Parity, Tag Parity errors
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* - clear the cache error log
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* - return previous value from RMIXL_PCR_L1D_CONFIG0
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*/
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static inline uint64_t
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rmixl_cache_err_dis(void)
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{
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uint64_t r;
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r = rmixl_mfcr(RMIXL_PCR_L1D_CONFIG0);
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rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r & ~0x2e);
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rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0);
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return r;
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}
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/*
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* rmixl_cache_err_restore:
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* - clear the cache error log, cache error overflow log,
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* and cache interrupt registers
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* - restore previous value to RMIXL_PCR_L1D_CONFIG0
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*/
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static inline void
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rmixl_cache_err_restore(uint64_t r)
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{
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rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG, 0);
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rmixl_mtcr(RMIXL_PCR_L1D_CACHE_ERROR_OVF_LO, 0);
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rmixl_mtcr(RMIXL_PCR_L1D_CACHE_INTERRUPT, 0);
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rmixl_mtcr(RMIXL_PCR_L1D_CONFIG0, r);
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}
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static inline uint64_t
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rmixl_cache_err_check(void)
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{
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return rmixl_mfcr(RMIXL_PCR_L1D_CACHE_ERROR_LOG);
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}
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static inline int
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rmixl_probe_4(volatile uint32_t *va)
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{
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uint32_t r;
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int err;
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int s;
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s = splhigh();
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r = rmixl_cache_err_dis();
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(void)*va; /* probe */
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err = rmixl_cache_err_check();
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rmixl_cache_err_restore(r);
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splx(s);
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return (err == 0);
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}
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#endif /* _MIPS_RMI_RMIXLVAR_H_ */
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