e544d50473
New fixup code. New common SPL code. New common interrupt code. Move related variables into structures. Cleanup locore (move MD variable into it). Kill StudlyCaps Use PCU for FPU
273 lines
7.6 KiB
C
273 lines
7.6 KiB
C
/* $NetBSD: pte.h,v 1.20 2011/02/20 07:45:47 matt Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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#ifndef __MIPS_PTE_H__
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#define __MIPS_PTE_H__
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#include <mips/mips1_pte.h>
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#include <mips/mips3_pte.h>
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#define PG_ASID 0x000000ff /* Address space ID */
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#ifndef _LOCORE
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#include <mips/cpu.h>
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typedef union pt_entry {
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uint32_t pt_entry; /* for copying, etc. */
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struct mips1_pte pt_mips1_pte; /* for getting to bits by name */
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struct mips3_pte pt_mips3_pte;
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} pt_entry_t;
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/*
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* Macros/inline functions to hide PTE format differences.
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*/
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#define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */
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bool pmap_is_page_ro_p(struct pmap *pmap, vaddr_t, uint32_t);
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/* MIPS1-only */
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#if defined(MIPS1) && !defined(MIPS3_PLUS)
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#define mips_pg_v(entry) ((entry) & MIPS1_PG_V)
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#define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED)
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#define mips_pg_m_bit() (MIPS1_PG_D)
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#define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */
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#define mips_pg_ro_bit() (MIPS1_PG_RO)
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#define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */
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#define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE)
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#define mips_pg_rwncpage_bit() (MIPS1_PG_RWNCPAGE)
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#define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE)
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#define mips_pg_cwncpage_bit() (MIPS1_PG_CWNCPAGE)
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#define mips_pg_global_bit() (MIPS1_PG_G)
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#define mips_pg_wired_bit() (MIPS1_PG_WIRED)
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#define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte))
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#define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va))
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#define mips_tlbpfn_to_paddr(x) mips1_tlbpfn_to_paddr((vaddr_t)(x))
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#define mips_paddr_to_tlbpfn(x) mips1_paddr_to_tlbpfn((x))
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#endif /* mips1 */
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/* MIPS3 (or greater) only */
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#if !defined(MIPS1) && defined(MIPS3_PLUS)
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#define mips_pg_v(entry) ((entry) & MIPS3_PG_V)
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#define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED)
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#define mips_pg_m_bit() (MIPS3_PG_D)
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#define mips_pg_rw_bit() (MIPS3_PG_D)
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#define mips_pg_ro_bit() (MIPS3_PG_RO)
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#define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE)
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#define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE)
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#define mips_pg_rwncpage_bit() (MIPS3_PG_RWNCPAGE)
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#define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE)
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#define mips_pg_cwncpage_bit() (MIPS3_PG_CWNCPAGE)
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#define mips_pg_global_bit() (MIPS3_PG_G)
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#define mips_pg_wired_bit() (MIPS3_PG_WIRED)
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#define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte))
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#define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va))
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#define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x))
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#define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x))
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#endif /* mips3 */
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/* MIPS1 and MIPS3 (or greater) */
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#if defined(MIPS1) && defined(MIPS3_PLUS)
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static __inline bool
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mips_pg_v(uint32_t entry),
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mips_pg_wired(uint32_t entry),
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PAGE_IS_RDONLY(uint32_t pte, vaddr_t va);
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static __inline uint32_t
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mips_pg_wired_bit(void) __pure,
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mips_pg_m_bit(void) __pure,
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mips_pg_ro_bit(void) __pure,
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mips_pg_rw_bit(void) __pure,
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mips_pg_ropage_bit(void) __pure,
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mips_pg_cwpage_bit(void) __pure,
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mips_pg_rwpage_bit(void) __pure,
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mips_pg_global_bit(void) __pure;
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static __inline paddr_t PTE_TO_PADDR(uint32_t pte) __pure;
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static __inline bool PAGE_IS_RDONLY(uint32_t pte, vaddr_t va) __pure;
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static __inline paddr_t mips_tlbpfn_to_paddr(uint32_t pfn) __pure;
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static __inline uint32_t mips_paddr_to_tlbpfn(paddr_t pa) __pure;
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static __inline bool
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mips_pg_v(uint32_t entry)
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{
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if (MIPS_HAS_R4K_MMU)
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return (entry & MIPS3_PG_V) != 0;
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return (entry & MIPS1_PG_V) != 0;
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}
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static __inline bool
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mips_pg_wired(uint32_t entry)
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{
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if (MIPS_HAS_R4K_MMU)
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return (entry & MIPS3_PG_WIRED) != 0;
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return (entry & MIPS1_PG_WIRED) != 0;
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}
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static __inline uint32_t
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mips_pg_m_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_D);
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return (MIPS1_PG_D);
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}
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static __inline unsigned int
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mips_pg_ro_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_RO);
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return (MIPS1_PG_RO);
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}
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static __inline unsigned int
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mips_pg_rw_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_D);
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return (MIPS1_PG_RW);
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}
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static __inline unsigned int
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mips_pg_ropage_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_ROPAGE);
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return (MIPS1_PG_RO);
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}
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static __inline unsigned int
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mips_pg_rwpage_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_RWPAGE);
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return (MIPS1_PG_RWPAGE);
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}
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static __inline unsigned int
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mips_pg_cwpage_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_CWPAGE);
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return (MIPS1_PG_CWPAGE);
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}
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static __inline unsigned int
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mips_pg_global_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_G);
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return (MIPS1_PG_G);
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}
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static __inline unsigned int
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mips_pg_wired_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_WIRED);
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return (MIPS1_PG_WIRED);
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}
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static __inline paddr_t
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PTE_TO_PADDR(uint32_t pte)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PTE_TO_PADDR(pte));
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return (MIPS1_PTE_TO_PADDR(pte));
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}
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static __inline bool
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PAGE_IS_RDONLY(uint32_t pte, vaddr_t va)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PAGE_IS_RDONLY(pte, va));
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return (MIPS1_PAGE_IS_RDONLY(pte, va));
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}
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static __inline paddr_t
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mips_tlbpfn_to_paddr(uint32_t pfn)
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{
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if (MIPS_HAS_R4K_MMU)
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return (mips3_tlbpfn_to_paddr(pfn));
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return (mips1_tlbpfn_to_paddr(pfn));
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}
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static __inline uint32_t
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mips_paddr_to_tlbpfn(paddr_t pa)
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{
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if (MIPS_HAS_R4K_MMU)
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return (mips3_paddr_to_tlbpfn(pa));
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return (mips1_paddr_to_tlbpfn(pa));
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}
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#endif
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#endif /* ! _LOCORE */
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* Kernel virtual address to page table entry and visa versa.
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*/
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#define kvtopte(va) \
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(Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT))
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#define ptetokv(pte) \
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((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
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extern pt_entry_t *Sysmap; /* kernel pte table */
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extern u_int Sysmapsize; /* number of pte's in Sysmap */
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#endif /* defined(_KERNEL) && !defined(_LOCORE) */
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#endif /* __MIPS_PTE_H__ */
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