e544d50473
New fixup code. New common SPL code. New common interrupt code. Move related variables into structures. Cleanup locore (move MD variable into it). Kill StudlyCaps Use PCU for FPU
379 lines
13 KiB
C
379 lines
13 KiB
C
/* $NetBSD: pmap.h,v 1.60 2011/02/20 07:45:47 matt Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)pmap.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Copyright (c) 1987 Carnegie-Mellon University
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)pmap.h 8.1 (Berkeley) 6/10/93
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*/
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#ifndef _MIPS_PMAP_H_
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#define _MIPS_PMAP_H_
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#ifdef _KERNEL_OPT
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#include "opt_multiprocessor.h"
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#endif
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#include <mips/cpuregs.h> /* for KSEG0 below */
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//#include <mips/pte.h>
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/*
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* The user address space is 2Gb (0x0 - 0x80000000).
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* User programs are laid out in memory as follows:
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* address
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* USRTEXT 0x00001000
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* USRDATA USRTEXT + text_size
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* USRSTACK 0x7FFFFFFF
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*
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* The user address space is mapped using a two level structure where
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* virtual address bits 30..22 are used to index into a segment table which
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* points to a page worth of PTEs (4096 page can hold 1024 PTEs).
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* Bits 21..12 are then used to index a PTE which describes a page within
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* a segment.
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*
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* The wired entries in the TLB will contain the following:
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* 0-1 (UPAGES) for curproc user struct and kernel stack.
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*
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* Note: The kernel doesn't use the same data structures as user programs.
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* All the PTE entries are stored in a single array in Sysmap which is
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* dynamically allocated at boot time.
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*/
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#define mips_trunc_seg(x) ((vaddr_t)(x) & ~SEGOFSET)
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#define mips_round_seg(x) (((vaddr_t)(x) + SEGOFSET) & ~SEGOFSET)
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#ifdef _LP64
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#define PMAP_SEGTABSIZE NSEGPG
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#else
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#define PMAP_SEGTABSIZE (1 << (31 - SEGSHIFT))
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#endif
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union pt_entry;
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union segtab {
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#ifdef _LP64
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union segtab *seg_seg[PMAP_SEGTABSIZE];
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#endif
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union pt_entry *seg_tab[PMAP_SEGTABSIZE];
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};
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/*
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* Structure defining an tlb entry data set.
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*/
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struct tlb {
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vaddr_t tlb_hi; /* should be 64 bits */
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uint32_t tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */
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uint32_t tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */
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};
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struct tlbmask {
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vaddr_t tlb_hi; /* should be 64 bits */
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uint32_t tlb_lo0; /* XXX maybe 64 bits (only 32 really used) */
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uint32_t tlb_lo1; /* XXX maybe 64 bits (only 32 really used) */
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uint32_t tlb_mask;
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};
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#ifdef _KERNEL
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struct pmap;
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typedef bool (*pte_callback_t)(struct pmap *, vaddr_t, vaddr_t,
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union pt_entry *, uintptr_t);
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union pt_entry *pmap_pte_lookup(struct pmap *, vaddr_t);
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union pt_entry *pmap_pte_reserve(struct pmap *, vaddr_t, int);
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void pmap_pte_process(struct pmap *, vaddr_t, vaddr_t, pte_callback_t,
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uintptr_t);
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void pmap_segtab_activate(struct pmap *, struct lwp *);
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void pmap_segtab_init(struct pmap *);
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void pmap_segtab_destroy(struct pmap *);
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#endif /* _KERNEL */
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/*
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* Per TLB (normally same as CPU) asid info
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*/
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struct pmap_asid_info {
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LIST_ENTRY(pmap_asid_info) pai_link;
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uint32_t pai_asid; /* TLB address space tag */
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};
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#define TLBINFO_LOCK(ti) mutex_spin_enter((ti)->ti_lock)
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#define TLBINFO_UNLOCK(ti) mutex_spin_exit((ti)->ti_lock)
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#define PMAP_PAI_ASIDVALID_P(pai, ti) ((pai)->pai_asid != 0)
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#define PMAP_PAI(pmap, ti) (&(pmap)->pm_pai[tlbinfo_index(ti)])
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#define PAI_PMAP(pai, ti) \
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((pmap_t)((intptr_t)(pai) \
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- offsetof(struct pmap, pm_pai[tlbinfo_index(ti)])))
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/*
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* Machine dependent pmap structure.
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*/
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struct pmap {
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#ifdef MULTIPROCESSOR
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volatile uint32_t pm_active; /* pmap was active on ... */
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volatile uint32_t pm_onproc; /* pmap is active on ... */
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volatile u_int pm_shootdown_pending;
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#endif
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union segtab *pm_segtab; /* pointers to pages of PTEs */
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u_int pm_count; /* pmap reference count */
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u_int pm_flags;
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#define PMAP_DEFERRED_ACTIVATE 0x0001
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struct pmap_statistics pm_stats; /* pmap statistics */
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struct pmap_asid_info pm_pai[1];
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};
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enum tlb_invalidate_op {
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TLBINV_NOBODY=0,
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TLBINV_ONE=1,
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TLBINV_ALLUSER=2,
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TLBINV_ALLKERNEL=3,
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TLBINV_ALL=4
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};
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struct pmap_tlb_info {
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char ti_name[8];
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uint32_t ti_asid_hint; /* probable next ASID to use */
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uint32_t ti_asids_free; /* # of ASIDs free */
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#define tlbinfo_noasids_p(ti) ((ti)->ti_asids_free == 0)
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kmutex_t *ti_lock;
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u_int ti_wired; /* # of wired TLB entries */
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uint32_t ti_asid_mask;
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uint32_t ti_asid_max;
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LIST_HEAD(, pmap_asid_info) ti_pais; /* list of active ASIDs */
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#ifdef MULTIPROCESSOR
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pmap_t ti_victim;
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uint32_t ti_synci_page_bitmap; /* page indices needing a syncicache */
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uint32_t ti_cpu_mask; /* bitmask of CPUs sharing this TLB */
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enum tlb_invalidate_op ti_tlbinvop;
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u_int ti_index;
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#define tlbinfo_index(ti) ((ti)->ti_index)
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struct evcnt ti_evcnt_synci_asts;
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struct evcnt ti_evcnt_synci_all;
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struct evcnt ti_evcnt_synci_pages;
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struct evcnt ti_evcnt_synci_deferred;
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struct evcnt ti_evcnt_synci_desired;
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struct evcnt ti_evcnt_synci_duplicate;
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#else
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#define tlbinfo_index(ti) (0)
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#endif
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struct evcnt ti_evcnt_asid_reinits;
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u_long ti_asid_bitmap[256 / (sizeof(u_long) * 8)];
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};
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#ifdef _KERNEL
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struct pmap_kernel {
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struct pmap kernel_pmap;
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#ifdef MULTIPROCESSOR
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struct pmap_asid_info kernel_pai[MAXCPUS-1];
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#endif
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};
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extern struct pmap_kernel kernel_pmap_store;
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extern struct pmap_tlb_info pmap_tlb0_info;
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#ifdef MULTIPROCESSOR
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extern struct pmap_tlb_info *pmap_tlbs[MAXCPUS];
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extern u_int pmap_ntlbs;
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#endif
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extern paddr_t mips_avail_start;
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extern paddr_t mips_avail_end;
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extern vaddr_t mips_virtual_end;
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#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define pmap_phys_address(x) mips_ptob(x)
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/*
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* Bootstrap the system enough to run with virtual memory.
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*/
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void pmap_bootstrap(void);
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void pmap_remove_all(pmap_t);
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void pmap_set_modified(paddr_t);
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void pmap_procwr(struct proc *, vaddr_t, size_t);
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#define PMAP_NEED_PROCWR
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#ifdef MULTIPROCESSOR
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void pmap_tlb_shootdown_process(void);
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bool pmap_tlb_shootdown_bystanders(pmap_t pmap);
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void pmap_tlb_info_attach(struct pmap_tlb_info *, struct cpu_info *);
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void pmap_tlb_syncicache_ast(struct cpu_info *);
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void pmap_tlb_syncicache_wanted(struct cpu_info *);
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void pmap_tlb_syncicache(vaddr_t, uint32_t);
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#endif
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void pmap_tlb_info_init(struct pmap_tlb_info *);
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void pmap_tlb_info_evcnt_attach(struct pmap_tlb_info *);
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void pmap_tlb_asid_acquire(pmap_t pmap, struct lwp *l);
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void pmap_tlb_asid_deactivate(pmap_t pmap);
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void pmap_tlb_asid_check(void);
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void pmap_tlb_asid_release_all(pmap_t pmap);
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int pmap_tlb_update_addr(pmap_t pmap, vaddr_t, uint32_t, bool);
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void pmap_tlb_invalidate_addr(pmap_t pmap, vaddr_t);
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/*
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* pmap_prefer() helps reduce virtual-coherency exceptions in
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* the virtually-indexed cache on mips3 CPUs.
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*/
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#ifdef MIPS3_PLUS
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#define PMAP_PREFER(pa, va, sz, td) pmap_prefer((pa), (va), (sz), (td))
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void pmap_prefer(vaddr_t, vaddr_t *, vsize_t, int);
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#endif /* MIPS3_PLUS */
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#define PMAP_STEAL_MEMORY /* enable pmap_steal_memory() */
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/*
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* Alternate mapping hooks for pool pages. Avoids thrashing the TLB.
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*/
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vaddr_t mips_pmap_map_poolpage(paddr_t);
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paddr_t mips_pmap_unmap_poolpage(vaddr_t);
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struct vm_page *mips_pmap_alloc_poolpage(int);
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#define PMAP_ALLOC_POOLPAGE(flags) mips_pmap_alloc_poolpage(flags)
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#define PMAP_MAP_POOLPAGE(pa) mips_pmap_map_poolpage(pa)
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#define PMAP_UNMAP_POOLPAGE(va) mips_pmap_unmap_poolpage(va)
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/*
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* Other hooks for the pool allocator.
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*/
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#ifdef _LP64
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#define POOL_VTOPHYS(va) (MIPS_KSEG0_P(va) \
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? MIPS_KSEG0_TO_PHYS(va) \
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: MIPS_XKPHYS_TO_PHYS(va))
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#else
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#define POOL_VTOPHYS(va) MIPS_KSEG0_TO_PHYS((vaddr_t)(va))
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#endif
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/*
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* Select CCA to use for unmanaged pages.
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*/
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#define PMAP_CCA_FOR_PA(pa) CCA_UNCACHED /* uncached */
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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#define PGC_NOCACHE 0x4000000000000000ULL
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#endif
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#define __HAVE_VM_PAGE_MD
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/*
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* pmap-specific data stored in the vm_page structure.
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*/
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/*
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* For each struct vm_page, there is a list of all currently valid virtual
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* mappings of that page. An entry is a pv_entry_t, the list is pv_table.
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* XXX really should do this as a part of the higher level code.
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*/
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typedef struct pv_entry {
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struct pv_entry *pv_next; /* next pv_entry */
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struct pmap *pv_pmap; /* pmap where mapping lies */
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vaddr_t pv_va; /* virtual address for mapping */
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} *pv_entry_t;
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#define PG_MD_UNCACHED 0x0001 /* page is mapped uncached */
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#define PG_MD_MODIFIED 0x0002 /* page has been modified */
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#define PG_MD_REFERENCED 0x0004 /* page has been recently referenced */
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#define PG_MD_POOLPAGE 0x0008 /* page is used as a poolpage */
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#define PG_MD_EXECPAGE 0x0010 /* page is exec mapped */
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#define PG_MD_CACHED_P(md) (((md)->pvh_attrs & PG_MD_UNCACHED) == 0)
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#define PG_MD_UNCACHED_P(md) (((md)->pvh_attrs & PG_MD_UNCACHED) != 0)
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#define PG_MD_MODIFIED_P(md) (((md)->pvh_attrs & PG_MD_MODIFIED) != 0)
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#define PG_MD_REFERENCED_P(md) (((md)->pvh_attrs & PG_MD_REFERENCED) != 0)
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#define PG_MD_POOLPAGE_P(md) (((md)->pvh_attrs & PG_MD_POOLPAGE) != 0)
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#define PG_MD_EXECPAGE_P(md) (((md)->pvh_attrs & PG_MD_EXECPAGE) != 0)
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struct vm_page_md {
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struct pv_entry pvh_first; /* pv_entry first */
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#ifdef MULTIPROCESSOR
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volatile u_int pvh_attrs; /* page attributes */
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kmutex_t *pvh_lock; /* pv list lock */
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#define PG_MD_PVLIST_LOCK_INIT(md) ((md)->pvh_lock = NULL)
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#define PG_MD_PVLIST_LOCKED_P(md) (mutex_owner((md)->pvh_lock) != 0)
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#define PG_MD_PVLIST_LOCK(md, lc) pmap_pvlist_lock((md), (lc))
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#define PG_MD_PVLIST_UNLOCK(md) mutex_spin_exit((md)->pvh_lock)
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#define PG_MD_PVLIST_GEN(md) ((uint16_t)((md)->pvh_attrs >> 16))
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#else
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u_int pvh_attrs; /* page attributes */
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#define PG_MD_PVLIST_LOCK_INIT(md) do { } while (/*CONSTCOND*/ 0)
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#define PG_MD_PVLIST_LOCKED_P(md) true
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#define PG_MD_PVLIST_LOCK(md, lc) (mutex_spin_enter(&pmap_pvlist_mutex), 0)
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#define PG_MD_PVLIST_UNLOCK(md) mutex_spin_exit(&pmap_pvlist_mutex)
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#define PG_MD_PVLIST_GEN(md) (0)
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#endif
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};
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#define VM_MDPAGE_INIT(pg) \
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do { \
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struct vm_page_md * const md = VM_PAGE_TO_MD(pg); \
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(md)->pvh_first.pv_next = NULL; \
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(md)->pvh_first.pv_pmap = NULL; \
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(md)->pvh_first.pv_va = VM_PAGE_TO_PHYS(pg); \
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PG_MD_PVLIST_LOCK_INIT(md); \
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(md)->pvh_attrs = 0; \
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} while (/* CONSTCOND */ 0)
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uint16_t pmap_pvlist_lock(struct vm_page_md *, bool);
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#endif /* _KERNEL */
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#endif /* _MIPS_PMAP_H_ */
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